Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 64 of 182
 3G: the UART is asynchronously enabled to paging receptions, as the UART is enabled for ~20 ms,
and then, if data are not received or sent, the UART is disabled for 2.5 s, and afterwards the
interface is enabled again
 Not registered: when a module is not registered with a network, the UART is enabled for ~20 ms,
and then, if data has not been received or sent, the UART is disabled for 2.5 s and afterwards the
interface is enabled again
The module active mode duration outside an active call depends on:
 Network parameters, related to the time interval for the paging block reception (minimum of ~11
ms)
 Duration of UART enable time in absence of data reception (~20 ms)
 The time period from the last data received at the serial port during the active mode: the module
does not enter idle mode until a timeout expires. The second parameter of the +UPSV AT
command configures this timeout, from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65000
2G-frames (i.e. 65000 x 4.615 ms = 300 s). The default value is 2000 2G-frames (i.e. 2000 x 4.615
ms = 9.2 s)
 The active mode duration can be extended indefinitely since every subsequent character received
during the active mode will reset and restart the timer.
 The timeout is ignored immediately after AT+UPSV=1 has been sent, so that the UART interface
is disabled and the module may enter idle mode immediately after the AT+UPSV=1 has been sent
The hardware flow-control output (CTS line) indicates when the UART interface is enabled (data can
be sent and received over the UART), if HW flow control is enabled, as illustrated in Figure 28.
time [s]
CTS ON
CTS OFF
UART disabled
~10 ms (min)
UART enabled
~9.2 s (default)
UART enabled
Data input
0.47- 2.10 s
Figure 28: CTS behavior with power saving enabled (AT+UPSV=1) and HW flow control enabled: the CTS output line indicates
when the UART interface of the module is enabled (CTS = ON = low level) or disabled (CTS = OFF = high level)
AT+UPSV=2: power saving enabled and controlled by the RTS line
This configuration can only be enabled with the module hardware flow control disabled by AT&K0
command.
The UART interface is immediately disabled after the DTE sets the RTS line to OFF.
Then the module automatically enters idle mode whenever possible according to any required activity
related to the network or any other required activity related to the functions / interfaces of the module.
The UART is disabled as long as the RTS line is held to OFF, but the UART is enabled in case the
module needs to transmit some data over the UART (e.g. URC).
When an OFF-to-ON transition occurs on the RTS input line, the UART is re-enabled and the module,
if it was in idle mode, switches from idle to active mode after ~20 ms: this is the UART and module
“wake-up time”.
If the RTS line is set to ON by the DTE, the module is not allowed to enter the low-power idle mode and
the UART is kept enabled.