Integration Manual
Table Of Contents
- Document Information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.9.1 Serial interfaces configuration
- 1.9.2 Asynchronous serial interface (UART)
- 1.9.2.1 UART features
- 1.9.2.2 UART signal behavior
- 1.9.2.3 UART and power-saving
- 1.9.2.4 UART application circuits
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TxD, RxD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TxD and RxD lines only (not using the complete V24 link)
- Additional considerations
- 1.9.3 USB interface
- 1.9.4 SPI interface
- 1.9.5 MUX protocol (3GPP TS 27.010)
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U2 module integration
- 1.15 Approvals
- 1.15.1 European Conformance CE mark
- 1.15.2 US Federal Communications Commission notice
- 1.15.3 Innovation, Science, Economic Development Canada notice
- 1.15.4 Australian Regulatory Compliance Mark
- 1.15.5 ICASA Certification
- 1.15.6 KCC Certification
- 1.15.7 ANATEL Certification
- 1.15.8 CCC Certification
- 1.15.9 Giteki Certification
- 2 Design-In
- 3 Features description
- 3.1 Network indication
- 3.2 Antenna detection
- 3.3 Jamming Detection
- 3.4 TCP/IP and UDP/IP
- 3.5 FTP
- 3.6 HTTP
- 3.7 SSL/TLS
- 3.8 Dual stack IPv4/IPv6
- 3.9 AssistNow clients and GNSS integration
- 3.10 Hybrid positioning and CellLocate®
- 3.11 Control Plane Aiding / Location Services (LCS)
- 3.12 Firmware update Over AT (FOAT)
- 3.13 Firmware update Over the Air (FOTA)
- 3.14 In-Band modem (eCall / ERA-GLONASS)
- 3.15 SIM Access Profile (SAP)
- 3.16 Smart Temperature Management
- 3.17 Bearer Independent Protocol
- 3.18 Multi-Level Precedence and Pre-emption Service
- 3.19 Network Friendly Mode
- 3.20 Power saving
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration from LISA-U1 to LISA-U2 series
- A.1 Checklist for migration
- A.2 Software migration
- A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules
- A.3 Hardware migration
- A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules
- A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series
- A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 42 of 182
Figure 19 describes the module’s power-off sequence, properly started by sending the AT+CPWROFF
command, allowing storage of current parameter settings in the module’s non-volatile memory and a
proper network detach:
When the +CPWROFF AT command is sent, the module starts the switch-off routine.
The module replies OK on the AT interface: the switch-off routine is in progress.
At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage
regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC
supply (V_BCKP).
Then, the module remains in power-off mode as long as a switch-on event does not occur (e.g.
applying a proper low level to the PWR_ON input, or applying a proper low level to the RESET_N
input), and enters not-powered mode if the supply is removed from the VCC pins.
VCC
V_BCKP
PWR_ON
RESET_N
V_INT
Internal Reset
System State
BB Pins State Operational
OFF
Tristate / Floating
ON
Operational → Tristate
AT+CPWROFF
sent to the module
0 s
~50 ms
~400 ms
OK
replied by the module
VCC
can be removed
Figure 19: LISA-U2 series Power-off sequence description
☞ The Internal Reset signal is not available on a module pin, but the application can monitor the
V_INT pin to sense the end of the LISA-U2 series power-off sequence.
☞ The duration of each phase in the LISA-U2 series modules’ switch-off routines can largely vary
from the values reported in Figure 19 (e.g. from tens of milliseconds up to tens of seconds),
depending on the application / network settings and the concurrent module activities.
☞ If the AT command +CPWROFF is issued to switch off the module over a multiplexer channel, the
completion of the module power-off sequence could require additionally up to 2.5 seconds after
the module OK reply. Therefore, if the Application Processor (AP) controls the VCC supply of the
module, the AP should disable the multiplexer protocol and then issue the AT+CPWROFF
command over the used AT interface, or otherwise the AP should issue the AT+CPWROFF
command over a multiplexer channel and wait additionally 2.5 seconds after OK reception before
removing the module VCC supply.
☞ Tri-stated pins are always subject to floating caused by noise: to prevent unwanted effects, fix
them with suitable pull-up or pull down resistors to stable voltage rails to fix their level when the
module is in power-down state.
☞ Any external signal connected to the UART, SPI/IPC, I
2
S and GPIOs must be tri-stated when the
module is in power-down mode, when the external reset is forced low and during the module power-
on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow
a proper boot of the module. If the external signals connected to the cellular module cannot be tri-
stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159,
or TS5A63157) between the two circuit connections and set to high impedance during module
power-down mode, when the external reset is forced low and during the power-on sequence.