Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 40 of 182
Figure 18 shows the modules power-on sequence from power-off mode, with the following phases:
 The external supply is still applied to the VCC inputs as it is assumed that the module has been
previously switched off by means of the AT+CPWROFF command: the V_BCKP output is internally
enabled as suitable VCC is present, the RESET_N is set to high logic level due to internal pull-up to
V_BCKP, the PWR_ON is set to high logic level due to an external pull-up.
 The PWR_ON input pin is set low for a valid time period, representing the start-up event.
 All the generic digital pins of the modules are tri-stated until the switch-on of their supply source
(V_INT): any external signal connected to the generic digital pins must be tri-stated or set low at
least until the activation of the V_INT supply output to avoid latch-up of circuits and allow a
complete boot of the module.
 The V_INT generic digital interfaces supply output is enabled by the integrated PMU.
 The internal reset signal is held low by the integrated power management unit: the baseband
processor core and all the digital pins of the modules are held in reset state, which is reported for
each pin of the module in the pin description table of the LISA-U2 series Data Sheet [1].
 When the internal reset signal is released by the integrated power management unit, the
processor core starts to configure the digital pins of the modules to each default operational state.
 The duration of these pins’ configuration phase differs within generic digital interfaces (3 s typical)
and USB interface due to specific enumeration timings (5 s typical, see section 1.9.3.1). The host
application processor should not send any AT command over the modules’ AT interfaces (USB,
UART) until the end of this interfaces’ configuration phase to allow a complete boot of the module.
 After the interfaces’ configuration phase, the application can start sending AT commands, and
the following starting procedure is suggested to check the effective completion of the module
internal boot sequence: send AT and wait for the response with a 30 second timeout, iterate it 4
times without resetting or removing the VCC supply of the module, and then run the application.
VCC
V_BCKP
PWR_ON
V_INT
Internal Reset
System State
BB Pads State
Internal Reset → Operational Operational
Tristate / Floating
Internal Reset
OFF
ON
Start-up
event
0 ms
~35 ms
~3 s
PWR_ON
can be set high
Start of interface
configuration
Generic digital interfaces
are configured
Figure 18: LISA-U2 series power-on sequence description
☞ The Internal Reset signal is not available on a module pin, but the application can monitor the
V_INT pin to sense the start of the power-on sequence.
☞ Any external signal connected to the UART interface, SPI/IPC interface, I
2
S interfaces and GPIOs
must be tri-stated when the module is in power-down mode, when the external reset is forced low
and during the module power-on sequence (at least for 3 seconds after the start-up event), to
avoid latch-up of circuits and let a proper boot of the module. If the external signals connected to
the cellular module cannot be tri-stated, insert a multi-channel digital switch (e.g. Texas
Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections
and set to high impedance during module power down mode, when the external reset is forced low,
and during the power-on sequence.