Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 Design-In Page 120 of 182
Rank
Function
Pin(s)
Layout
Remarks
1
st
RF Antenna
Main RF input/output
Very Important
Design for 50  characteristic
impedance. See section 2.2.1.1
RF input for Rx
diversity
Very Important
Design for 50  characteristic
impedance. See section 2.2.1.1
2
nd
Main DC Supply
Very Important
VCC line should be wide and short. Route
away from sensitive analog signals.
See section 2.2.1.2
3
rd
USB Signals
Very Important
Route USB_D+ and USB_D- as
differential lines: design for 90 
differential impedance (Z
0
) and design
for 30  common mode impedance (Z
CM
).
See section 2.2.1.3
4
th
Ground
GND
Careful Layout
Provide proper grounding.
See section 2.2.1.4
5
th
Sensitive Pin:
Careful Layout
Avoid coupling with noisy signals.
See section 2.2.1.5
Backup Voltage
V_BCKP
Power-On
PWR_ON
6
th
High-speed digital pins:
Careful Layout
Avoid coupling with sensitive signals.
See section 2.2.1.6
SPI Signals
SPI_SCLK, SPI_MISO,
SPI_MOSI, SPI_SRDY,
SPI_MRDY
Clock Output
CODEC_CLK
7
th
Digital pins and supplies:
Common
Practice
Follow common practice rules for digital
pin routing.
See section 2.2.1.7
SIM Card Interface
VSIM, SIM_CLK, SIM_IO,
SIM_RST
Digital Audio
I2S_CLK, I2S_RXD, I2S_TXD,
I2S_WA, I2S1_CLK, I2S1_RXD,
I2S1_TXD, I2S1_WA
DDC
SCL, SDA
UART
TXD, RXD, CTS, RTS, DSR, RI,
DCD, DTR
External Reset
RESET_N
General Purpose I/O
GPIO1, GPIO2, GPIO3, GPIO4,
GPIO5, GPIO6, GPIO7, GPIO8,
GPIO9, GPIO10, GPIO11, GPIO12,
GPIO13, GPIO14
USB detection
VUSB_DET
Supply for Interfaces
V_INT
Table 45: Pin list in order of decreasing importance for layout design
VCC
USB_D-
USB_D+
ANT
ANT_DIV