Integration Manual
Table Of Contents
- Document Information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.9.1 Serial interfaces configuration
- 1.9.2 Asynchronous serial interface (UART)
- 1.9.2.1 UART features
- 1.9.2.2 UART signal behavior
- 1.9.2.3 UART and power-saving
- 1.9.2.4 UART application circuits
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TxD, RxD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TxD and RxD lines only (not using the complete V24 link)
- Additional considerations
- 1.9.3 USB interface
- 1.9.4 SPI interface
- 1.9.5 MUX protocol (3GPP TS 27.010)
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U2 module integration
- 1.15 Approvals
- 1.15.1 European Conformance CE mark
- 1.15.2 US Federal Communications Commission notice
- 1.15.3 Innovation, Science, Economic Development Canada notice
- 1.15.4 Australian Regulatory Compliance Mark
- 1.15.5 ICASA Certification
- 1.15.6 KCC Certification
- 1.15.7 ANATEL Certification
- 1.15.8 CCC Certification
- 1.15.9 Giteki Certification
- 2 Design-In
- 3 Features description
- 3.1 Network indication
- 3.2 Antenna detection
- 3.3 Jamming Detection
- 3.4 TCP/IP and UDP/IP
- 3.5 FTP
- 3.6 HTTP
- 3.7 SSL/TLS
- 3.8 Dual stack IPv4/IPv6
- 3.9 AssistNow clients and GNSS integration
- 3.10 Hybrid positioning and CellLocate®
- 3.11 Control Plane Aiding / Location Services (LCS)
- 3.12 Firmware update Over AT (FOAT)
- 3.13 Firmware update Over the Air (FOTA)
- 3.14 In-Band modem (eCall / ERA-GLONASS)
- 3.15 SIM Access Profile (SAP)
- 3.16 Smart Temperature Management
- 3.17 Bearer Independent Protocol
- 3.18 Multi-Level Precedence and Pre-emption Service
- 3.19 Network Friendly Mode
- 3.20 Power saving
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration from LISA-U1 to LISA-U2 series
- A.1 Checklist for migration
- A.2 Software migration
- A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules
- A.3 Hardware migration
- A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules
- A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series
- A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 12 of 182
Function
Pin
Module
No
I/O
Description
Remarks
SPI
SPI_MISO
All
57
O
SPI Data Line
Output
Module Output: module runs as an SPI slave.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
Idle high.
See section 1.9.4
SPI_MOSI
All
56
I
SPI Data Line
Input
Module Input: module runs as an SPI slave.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
Idle high.
Internal active pull-up to V_INT (1.8 V) enabled.
See section 1.9.4
SPI_SCLK
All
55
I
SPI Serial Clock
Input
Module Input: module runs as an SPI slave.
Idle low (CPOL=0).
Internal active pull-down to GND enabled.
See section 1.9.4
SPI_SRDY
All
58
O
SPI Slave Ready
Output
Module Output: module runs as an SPI slave.
Idle low.
See section 1.9.4
SPI_MRDY
All
59
I
SPI Master Ready
Input
Module Input: module runs as an SPI slave.
Idle low.
Internal active pull- down to GND enabled.
See section 1.9.4
DDC
SCL
All
45
O
I
2
C bus clock line
Fixed open drain. External pull-up required.
See section 1.10
SDA
All
46
I/O
I
2
C bus data line
Fixed open drain. External pull-up required.
See section 1.10
UART
RxD
All
16
O
UART data output
Circuit 104 (RxD) in ITU-T V.24.
Provide access to the pin for FW update and
debugging if the USB interface is connected
to the application processor.
See section 1.9.2
TxD
All
15
I
UART data input
Circuit 103 (TxD) in ITU-T V.24.
Internal active pull-up to V_INT (1.8 V) enabled.
Provide access to the pin for FW update and
debugging if the USB interface is connected
to the application processor.
See section 1.9.2
CTS
All
14
O
UART clear to
send output
Circuit 106 (CTS) in ITU-T V.24.
Provide access to the pin for debugging if the
USB interface is connected to the application
processor.
See section 1.9.2
RTS
All
13
I
UART ready to
send input
Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT (1.8 V) enabled.
Provide access to the pin for debugging if the
USB interface is connected to the application
processor.
See section 1.9.2
DSR
All
9
O
UART data set
ready output
Circuit 107 (DSR) in ITU-T V.24.
See section 1.9.2
RI
All
10
O
UART ring
indicator output
Circuit 125 (RI) in ITU-T V.24.
See section 1.9.2
DTR
All
12
I
UART data
terminal ready
input
Circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up to V_INT (1.8 V) enabled.
See section 1.9.2
DCD
All
11
O
UART data carrier
detect output
Circuit 109 (DCD) in ITU-T V.24.
See section 1.9.2