Integration Manual
Table Of Contents
- Document Information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.9.1 Serial interfaces configuration
- 1.9.2 Asynchronous serial interface (UART)
- 1.9.2.1 UART features
- 1.9.2.2 UART signal behavior
- 1.9.2.3 UART and power-saving
- 1.9.2.4 UART application circuits
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TxD, RxD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TxD and RxD lines only (not using the complete V24 link)
- Additional considerations
- 1.9.3 USB interface
- 1.9.4 SPI interface
- 1.9.5 MUX protocol (3GPP TS 27.010)
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U2 module integration
- 1.15 Approvals
- 1.15.1 European Conformance CE mark
- 1.15.2 US Federal Communications Commission notice
- 1.15.3 Innovation, Science, Economic Development Canada notice
- 1.15.4 Australian Regulatory Compliance Mark
- 1.15.5 ICASA Certification
- 1.15.6 KCC Certification
- 1.15.7 ANATEL Certification
- 1.15.8 CCC Certification
- 1.15.9 Giteki Certification
- 2 Design-In
- 3 Features description
- 3.1 Network indication
- 3.2 Antenna detection
- 3.3 Jamming Detection
- 3.4 TCP/IP and UDP/IP
- 3.5 FTP
- 3.6 HTTP
- 3.7 SSL/TLS
- 3.8 Dual stack IPv4/IPv6
- 3.9 AssistNow clients and GNSS integration
- 3.10 Hybrid positioning and CellLocate®
- 3.11 Control Plane Aiding / Location Services (LCS)
- 3.12 Firmware update Over AT (FOAT)
- 3.13 Firmware update Over the Air (FOTA)
- 3.14 In-Band modem (eCall / ERA-GLONASS)
- 3.15 SIM Access Profile (SAP)
- 3.16 Smart Temperature Management
- 3.17 Bearer Independent Protocol
- 3.18 Multi-Level Precedence and Pre-emption Service
- 3.19 Network Friendly Mode
- 3.20 Power saving
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration from LISA-U1 to LISA-U2 series
- A.1 Checklist for migration
- A.2 Software migration
- A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules
- A.3 Hardware migration
- A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules
- A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series
- A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 107 of 182
1.14 Schematic for LISA-U2 module integration
Figure 54 is an example of a schematic diagram where the LISA-U2 series module is integrated into
an application board, using all the interfaces of the module.
TXD
RXD
RTS
CTS
DTR
DSR
RI
DCD
GND
15 TXD
12 DTR
16 RXD
13 RTS
14 CTS
9 DSR
10 RI
11 DCD
GND
3V8
GND
LISA-U2 series
62 VCC
63 VCC
61 VCC
+
100µF
2 V_BCKP
MOSI
MISO
SCLK
Interrupt
GPIO
GND
56
SPI_MOSI
59
SPI_MRDY
57
SPI_MISO
55
SPI_SCLK
58
SPI_SRDY
GND
VBUS
D+
D-
GND
18
VUSB_DET
27
USB_D+
26
USB_D-
GND
100nF
5RSVD
74ANT_DIV
GND
RTC
back-
up
u-blox GNSS
1.8V Receiver
4.7k
OUTIN
GND
LDO Regulator
SHDN
SDA
SCL
4.7k
3V8 1V8_GPS
SDA2
SCL2
GPIO3
GPIO4
TxD1
EXTINT0
46
45
23
24
47k
VCC
GPIO2
21
ANT
68
Main Tx/Rx
Antenna
1.8V DTE
1.8V SPI Master
USB 2.0 Host
20 GPIO1
3V8
Network
Indicator
22
RESET_N
Ferrite
Bead
47pF
Application
Processor
Open
Drain
Output
19 PWR_ON
100kΩ
Open
Drain
Output
0Ω
0Ω
TP
TP
0Ω
0Ω
TP
TP
1.8V Digital
Audio Device
I2S_RXD
I2S_CLK
I2S Data Output
I2S Clock
I2S_TXD
I2S_WA
I2S Data Input
I2S Word
Alligment
44
43
42
41
Rx Diversity
Antenna
LISA-U230 only
47pF
SIM Card Holder
CCVCC (C1)
CCVPP (C6)
CCIO (C7)
CCCLK (C3)
CCRST (C2)
GND (C5)
47pF47pF 100nF
50VSIM
48SIM_IO
47SIM_CLK
49SIM_RST
47pF
SW1
SW2
4V_INT
51GPIO5
470k
1k
ESD ESD ESD ESD ESD ESD
V_INT
220nF
V_INT
BCLK
LRCLK
10µF1µF
Audio Codec
MAX9860
SDIN
SDOUT
SDA
SCL
53I2S1_CLK
54I2S1_WA
40I2S1_TXD
39I2S1_RXD
52CODEC_CLK MCLK
IRQn
10k
100nF
VDD
SPK
OUTP
OUTN
MIC
MICBIAS
1µF
2.2k
1µF
1µF
MICLN
MICLP
MICGND
2.2k
ESD ESD
27pF27pF
V_INT
EMI
EMI
10nF10nF
EMI
EMI
ESD ESD
27pF27pF10nF10nF
330µF
10nF100nF 15pF 68pF
Ferrite
Bead
Figure 54: Example of a schematic diagram to integrate LISA-U2 modules in an application board, using all the interfaces