Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 104 of 182
Pin
Name
Description
Remarks
57
SPI_MISO /
GPIO12
SPI Data Line Output /
GPIO
By default, the pin is configured as SPI Data Line Output:
 Shift data on rising clock edge (CPHA=1)
 Latch data on falling clock edge (CPHA=1)
 Idle high
Can be alternatively configured by the +UGPIOC command as:
 Output
 Input
 Pad disabled
58
SPI_SRDY /
GPIO13
SPI Slave Ready /
GPIO
By default, the pin is configured as SPI Slave Ready Output:
 Idle low
Can be alternatively configured by the +UGPIOC command as:
 Output
 Input
 Module Status Indication
 Pad disabled
59
SPI_MRDY /
GPIO14
SPI Master Ready /
GPIO
By default, the pin is configured as SPI Master Ready Input:
 Idle low
 Internal active pull-down to GND enabled
Can be alternatively configured by the +UGPIOC command as:
 Output
 Input
 Module Operating Mode Indication
 Pad disabled
Table 42: GPIO pin configurations
☞ The GPIO pins’ ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F).
Higher protection levels could be required if the lines are externally accessible on the application
board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS
CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points.
An application circuit for a typical GPIOs usage is described in Figure 52:
 Network indication function provided by the GPIO1 pin
 GNSS supply enable function provided by the GPIO2 pin
 GNSS data ready function provided by the GPIO3 pin
 GNSS RTC sharing function provided by the GPIO4 pin
 SIM card detection function provided by the GPIO5 pin
☞ Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ resistor
on the board in series with the GPIO.
☞ If the GPIO pins are not used, they can be left unconnected on the application board.
☞ Any external signal connected to GPIOs must be tri-stated when the module is in power-down
mode, when the external reset is forced low, and during the module power-on sequence (at least
for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a proper boot of the
module. If the external signals connected to the module cannot be tri-stated, insert a multi-
channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157)
between the two-circuit connections and set to high impedance during module power-down mode,
when the external reset is forced low, and during the power-on sequence.