Integration Manual

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Table Of Contents

Document Information
Contents
1 System description
- 1.1 Overview
- 1.2 Architecture
  - 1.2.1 Functional blocks
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
  - 1.8.1 (U)SIM application circuits
- 1.9 Serial communication
- 1.10 DDC (I2C) interface
  - 1.10.1 Overview
  - 1.10.2 DDC application circuits
    - 1.10.2.1 General considerations
    - 1.10.2.2 Connection with u-blox GNSS receivers
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U2 module integration
- 1.15 Approvals
2 Design-In
- 2.1 Design-in checklist
- 2.2 Design Guidelines for Layout
- 2.3 Thermal guidelines
- 2.4 Antenna guidelines
- 2.5 ESD guidelines
3 Features description
- 3.1 Network indication
- 3.2 Antenna detection
- 3.3 Jamming Detection
- 3.4 TCP/IP and UDP/IP
  - 3.4.1 Multiple PDP contexts and sockets
- 3.5 FTP
- 3.6 HTTP
- 3.7 SSL/TLS
- 3.8 Dual stack IPv4/IPv6
- 3.9 AssistNow clients and GNSS integration
- 3.10 Hybrid positioning and CellLocate®
  - 3.10.1 Positioning through cellular information: CellLocate®
  - 3.10.2 Hybrid positioning
- 3.11 Control Plane Aiding / Location Services (LCS)
- 3.12 Firmware update Over AT (FOAT)
  - 3.12.1 Overview
  - 3.12.2 FOAT procedure
- 3.13 Firmware update Over the Air (FOTA)
- 3.14 In-Band modem (eCall / ERA-GLONASS)
- 3.15 SIM Access Profile (SAP)
- 3.16 Smart Temperature Management
  - 3.16.1 Smart Temperature Supervisor (STS)
  - 3.16.2 Threshold definitions
- 3.17 Bearer Independent Protocol
- 3.18 Multi-Level Precedence and Pre-emption Service
- 3.19 Network Friendly Mode
- 3.20 Power saving
4 Handling and soldering
- 4.1 Packaging, shipping, storage and moisture preconditioning
- 4.2 Soldering
5 Product Testing
- 5.1 u-blox in-series production test
- 5.2 Test parameters for OEM manufacturer
  - 5.2.1 ‘Go/No go’ tests for integrated devices
  - 5.2.2 Functional tests providing RF operation
Appendix
A Migration from LISA-U1 to LISA-U2 series
A.1 Checklist for migration
A.2 Software migration
A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules
A.3 Hardware migration
A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules
A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series
A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series
B Glossary
Related documents
Revision history
Contact

LISA-U2 series - System Integration Manual

UBX-13001118 - R25 System description Page 103 of 182

Name

Description

Remarks

GPIO3

GPIO

By default, the pin is configured to provide GNSS Data Ready function.

Can be alternatively configured by the +UGPIOC command as:

 Output

 Input

 Network Status Indication

 GNSS Supply Enable

 Pad disabled

GPIO4

GPIO

By default, the pin is configured to provide GNSS RTC sharing function.

Can be alternatively configured by the +UGPIOC command as:

 Output

 Input

 Network Status Indication

 GNSS Supply Enable

 Pad disabled

GPIO5

GPIO

By default, the pin is configured to provide SIM card detection function.

Can be alternatively configured by the +UGPIOC command as:

 Output

 Input

 Network Status Indication

 GNSS Supply Enable

 Module Operating Mode Indication

 Pad disabled

I2S1_RXD /

GPIO6

S receive data /

GPIO

By default, the pin is configured as 2

S receive data input.

Can be alternatively configured by the +UGPIOC, +USPM commands as:

 Output

 Input

 Pad disabled

I2S1_TXD /

GPIO7

S transmit data /

GPIO

By default, the pin is configured as 2

S transmit data output.

Can be alternatively configured by the +UGPIOC, +USPM commands as:

 Output

 Input

 Pad disabled

I2S1_CLK /

GPIO8

S clock /

GPIO

By default, the pin is configured as 2

S clock input/output.

Can be alternatively configured by the +UGPIOC, +USPM commands as:

 Output

 Input

 Pad disabled

I2S1_WA /

GPIO9

S word alignment /

GPIO

By default, the pin is configured as 2

S word alignment input/output.

Can be alternatively configured by the +UGPIOC, +USPM commands as:

 Output

 Input

 Pad disabled

SPI_SCLK /

GPIO10

SPI Serial Clock /

GPIO

By default, the pin is configured as SPI Serial Clock Input:

 Idle low (CPOL=0)

 Internal active pull-down to GND enabled

Can be alternatively configured by the +UGPIOC command as:

 Output

 Input

 Pad disabled

SPI_MOSI /

GPIO11

SPI Data Line /

GPIO

By default, the pin is configured as SPI Data Line Input:

 Shift data on rising clock edge (CPHA=1)

 Latch data on falling clock edge (CPHA=1)

 Idle high

 Internal active pull-up to V_INT enabled

Can be alternatively configured by the +UGPIOC command as:

 Output

 Input

 Pad disabled