Installation Instructions

LISA-U2 series - System Integration Manual
UBX-13001118 - R19 Early Production Information System description
Page 42 of 175
1.6.3 Module reset
LISA-U2 series modules can be properly reset (rebooted) by:
 AT+CFUN command (see the u-blox AT Commands Manual [2] for more details).
This command causes an “internal” or “software” reset of the module, causing an asynchronous reset of the
module baseband processor, excluding the integrated Power Management Unit and the RTC internal block. The
V_INT interfaces supply is enabled and each digital pin is set in its internal reset state (reported in the pin
description table in LISA-U2 series Data Sheet [1]), the V_BCKP supply and the RTC block are enabled.
Forcing an “internal” or “software” reset, the current parameter settings are saved in the module’s non-volatile
memory and a proper network detach is performed: this is the proper way to reset the modules.
An abrupt hardware reset occurs on LISA-U2 series modules when a low level is applied on the RESET_N input
pin for a specific time period. In this case, the current parameter settings are not saved in the module’s
non-volatile memory and a proper network detach is not performed.
It is highly recommended to avoid an abrupt “external” or “hardware” reset of the module by forcing a
low level on the RESET_N input pin during the module normal operation: the RESET_N line should be set
low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific
AT command after a time period longer than the one defined in the u-blox AT Commands Manual [2].
When a low level is applied to the RESET_N input, it causes an “external” or “hardware” reset of the module,
with an asynchronous abrupt reset of the entire module, including the integrated Power Management Unit,
except for the RTC internal block. The V_INT interfaces supply is switched off and all the digital pins of the
modules are tri-stated, but the V_BCKP supply and the RTC block are enabled.
Forcing an “external” or “hardware” reset, the current parameter settings are not saved in the module’s
non-volatile memory and a proper network detach is not performed.
When RESET_N is released from the low level, the module automatically starts its power-on sequence from the
reset state. The same procedure is followed for the module reset via AT command after having performed the
network detach and the parameter saving in non-volatile memory.
Name
Description
Remarks
RESET_N
External reset input
Internal 10 k pull-up to V_BCKP
Table 18: Reset pin
The RESET_N pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher
protection level could be required if the line is externally accessible on the application board. Higher
protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor
array) on the line connected to this pin, close to accessible point.
For more details about RESET_N circuit precautions for ESD immunity, see section 2.5.3.
The electrical characteristics of RESET_N are different from the other digital I/O interfaces. The detailed electrical
characteristics are described in LISA-U2 series Data Sheet [1].
RESET_N is pulled high by an integrated 10 k pull-up resistor to V_BCKP. Therefore an external pull-up is not
required on the application board.
Following are some typical examples of application circuits using the RESET_N input pin.
The simplest way to reset the module is to use a push button that shorts the RESET_N pin to ground.