User's Manual

LISA-U1/LISA-H1 series - System Integration Manual
3G.G2-HW-10002-2 Advance Information System description
Page 60 of 116
4. When the master is ready to send, it will signalize this by activating SPI_MRDY. This is optional, when
SPI_MRDY is low before
5. The slave indicates immediately after a transfer termination that it wants to start transmission again. In this
case the slave will raise SPI_SRDY again. The SPI_MRDY line can be either high or low: the master has only
to ensure that the SPI_SRDY change will be detected correctly via interrupt
For more details regarding IPC communication protocol please refer to SPI Application Note [18].
1.9.4.3 IPC application circuit
SPI_MOSI is the data line input for the module since it runs as SPI slave: it must be connected to the data line
output (MOSI) of the application processor that runs as an SPI master.
SPI_MISO is the data line output for the module since it runs as SPI slave: it must be connected to the data line
input (MISO) of the application processor that runs as an SPI master.
SPI_SCLK is the clock input for the module since it runs as SPI slave: it must be connected to the clock line
output (SCLK) of the application processor that runs as an SPI master.
SPI_MRDY is an input for the module able to detect an external interrupt which comes from the application
processor.
SPI_SRDY is an output for the module, and the application processor should be able to detect an external
interrupt which comes from the module on its connected pin.
Signal integrity of the high speed data lines may be degraded if the PCB layout is not optimal, especially when
the SPI lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity.
LISA-U1/LISA-H1 series
(SPI slave)
MOSI
Application Processor
(SPI master)
MISO
SCLK
Interrupt
GPIO
GND
56
SPI_MOSI
59
SPI_MRDY
57
SPI_MISO
55
SPI_SCLK
58
SPI_SRDY
GND
Figure 35: IPC Interface application circuit
If direct access to the USB or the UART interfaces of the module is not provided, it is recommended to
provide direct access to the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY lines of the
module for debug purpose: testpoints can be added on the lines to accommodate the access and a 0 Ω
series resistor must be mounted on each line to detach the module pin from any other connected
device.
If the SPI/IPC interface is not used, the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY pins
can be left unconnected.
1.9.5 MUX Protocol (3GPP 27.010)
The LISA-U1/LISA-H1 series module has a software layer with MUX functionality, 3GPP TS 27.010 Multiplexer
Protocol [6], available on the UART and on the SPI physical link.
This is a data link protocol (layer 2 of OSI model) which uses HDLC-like framing and operates between the
module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used