User's Manual

LISA-U1/LISA-H1 series - System Integration Manual
3G.G2-HW-10002-2 Advance Information Design-In
Page 103 of 116
 It is recommended to keep the connection line to RESET_N as short as possible
LISA-U1/LISA-H1
series
2
V_BCKP
22
RESET_N
Reset
push button
ESD
Open
Drain
Output
Application
Processor
LISA-U1/LISA-H1
series
2
V_BCKP
22
RESET_N
Rint
Rint
FB1
C1
FB2
C2
Figure 59: RESET_N application circuits for ESD immunity test
Reference
Description
Remarks
ESD
Varistor for ESD protection.
CT0402S14AHSG - EPCOS
C1, C2
47 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H470JA01 - Murata
FB1, FB2
Chip Ferrite Bead for Noise/EMI Suppression
BLM15HD182SN1 - Murata
Rint
10 kΩ Resistor 0402 5% 0.1 W
Internal pull-up resistor
Table 38: Example of components as ESD immunity test precautions for the RESET_N line
Sensitive interface is the SIM interface (VSIM pin, SIM_RST pin, SIM_IO pin, SIM_CLK pin):
 A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) have to be mounted on the lines connected to
VSIM, SIM_RST, SIM_IO and SIM_CLK to assure SIM interface functionality when an electrostatic discharge
is applied to the application board
 It is suggested to use as short as possible connection lines at SIM pins
2.5.2 Antenna interface precautions
The antenna interface ANT could be involved in the ESD immunity test criticality depending on the application
board handling. Antenna precaution is herein suggested.
 If the device implements an embedded antenna and the device insulating enclosure avoids air discharge up
to +8 kV / -8 kV to the antenna interface, no further precautions to ESD immunity test should be needed
 If the device implements an external antenna and the antenna and its connecting cable are provided with a
completely insulating enclosure to avoid air discharge up to +8 kV / -8 kV to the whole antenna and cable
surfaces, no further precautions to ESD immunity test should be needed