User Guide
Table Of Contents
- Document information
- Contents
- 1 LARA-R2 / LARA-R6 modules description
- 2 Migration between LARA modules
- 2.1 Overview
- 2.2 Pin-out comparison between LARA modules
- 2.3 Interfaces comparison between LARA modules
- 2.3.1 VCC module supply input
- 2.3.2 V_INT 1.8 V supply output
- 2.3.3 V_BCKP RTC supply input/output
- 2.3.4 Cellular RF interfaces
- 2.3.5 System control interfaces
- 2.3.6 SIM interface
- 2.3.7 UART interfaces
- 2.3.8 USB interface
- 2.3.9 I2C interface
- 2.3.10 Digital audio interface
- 2.3.11 Clock output
- 2.3.12 GPIOs
- 2.3.13 Antenna dynamic tuning
- 2.3.14 Reserved pins
- 2.3.15 Other considerations and test points
- 2.4 Schematic for LARA modules integration
- Appendix
- A Glossary
- Related documents
- Revision history
- Contact
LARA-R2/R6 migration guide - Application note
UBX-21010015 - R02 Migration between LARA modules Page 7 of 25
C1-Public
2 Migration between LARA modules
2.1 Overview
The u-blox LARA form factor (26.0 x 24.0 mm, 100-pin LGA) includes the following series of modules,
with compatible pin assignments as described in
Figure 1, so that the modules can be alternatively
mounted on a single application PCB using exactly the same copper, solder resist and paste mask.
64 63
61 60
58 57
55 54
22
50
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
CTS
RTS
DCD
RI
V_INT
V_BCKP
GND
GPIO6
RESET_N
GPIO1
PWR_ON
RXD
TXD
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
3
20
17
14
9
6
23
25 26
28 29
31 32
24
27
30
43
44
46
47
49
52
53
33
35
36
38
39
41
42
51
48
45
40
37
34
59
62
56
GND
GND
DSR
DTR
GND
VUSB_DET
GND
USB_D-
USB_D+
RSVD
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
GND
VCC
VCC
RSVD
I2S_TXD
I2S_CLK
SIM_CLK
SIM_IO
VSIM
GPIO5
VCC
SIM_RST
I2S_RXD
I2S_WA
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT2
ANT1
LARA-R2
Top view
Pin 65-96: GND
99
100
97
98
RSVD
RSVD
HSIC_STRB
HSIC_DATA
HOST_SELECT
SDIO_D2
SDIO_CMD
SDIO_D0
SDIO_D1
SDIO_D3
SDIO_CLK
64 63
61 60
58 57
55 54
22
50
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
CTS
RTS
DCD
RI
V_INT
RSVD
GND
GPIO6
RESET_N
GPIO1
PWR_ON
RXD
TXD
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
3
20
17
14
9
6
23
25 26
28 29
31 32
24
27
30
43
44
46
47
49
52
53
33
35
36
38
39
41
42
51
48
45
40
37
34
59
62
56
GND
GND
DSR
DTR
GND
VUSB_DET
GND
USB_D-
USB_D+
RSVD
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
GND
VCC
VCC
RSVD
I2S_TXD
I2S_CLK
SIM_CLK
SIM_IO
VSIM
GPIO5
VCC
SIM_RST
I2S_RXD
I2S_WA
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT2
ANT1
LARA-R6
Top view
Pin 65-96: GND
99
100
97
98
RFCTL2
or RSVD
RFCTL1
or RSVD
RSVD
RSVD
GND
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Figure 1: LARA-R2 and LARA-R6 series modules’ layout and pinout
Table 4 summarizes the interfaces supported by LARA series modules:
LARA-R2 series
LARA-R6 series
VCC module supply input
●
●
V_INT 1.8V supply output
●
●
V_BCKP RTC supply input/output
●
ANT1 main RF input/output
●
●
ANT2 RF Rx diversity input
●
●
ANT_DET antenna detection input
●
●
Antenna dynamic tuning (RFCTL1 / RFCTL2)
●
4
PWR_ON input
●
●
RESET_N input
●
●
SIM interface
●
●
SIM detection
●
●
Main primary 8-wire UART
●
●
Auxiliary secondary 4-wire UART
●
Auxiliary secondary 2-wire UART
●
4
LARA-R6401 and LARA-R6401D only