Data Sheet

JODY-W2 series - Data sheet
UBX-18017567 - R07 Interfaces Page 9 of 46
C1 - Public
2 Interfaces
2.1 Host interface configuration
The JODY-W2 series provides two configuration pins, CONFIG[0] and CONFIG[1], for selecting the
host interface configuration and additional configuration pins are used to set parameters following a
reset. To set a configuration bit to 0, attach a 100 kΩ resistor to GND. No external pull-up resistor is
required to set a configuration bit to 1. Table 4 Table 5 show all strapping options.
CONFIG[1] CONFIG[0] Wi-Fi Bluetooth Firmware download Number of SDIO functions
1 0 SDIO UART SDIO+UART(parallel/Serial) 1 (Wi-Fi)
1 1 SDIO SDIO SDIO+SDIO(parallel/Serial) 2 (Wi-Fi, Bluetooth)
Table 4: Host interface configuration options
Additional configuration pins are listed in Table 5.
Name Pin Description
PCM_OUT 17 Set high during reset.
BT_UART_RTS 38 Set high during reset.
LTE_COEX_TX 13 Set high during reset.
BT_UART_TX 36 Set low during reset. A 51 kΩ pull down resistor is implemented on the module.
Table 5: Additional configuration pins
2.2 SDIO interface
The SDIO device interface conforms to the industry standard SDIO 3.0 specification (UHS-I, up to
104 MByte/s). The interface allows host controllers to access the Wi-Fi, and optionally Bluetooth,
functions of JODY-W2 series modules using the SDIO bus protocol. The interface supports 4-bit SDIO
transfer mode at the full clock range up to 208 MHz. For SDIO 2.0 running at 25 MHz and 50 MHz clock
frequencies. Only a signal voltage of 1.8 V is supported for all bus speed modes.
Bus speed mode Max clock frequency [MHz] Signal voltage [V] Max. bus speed [MB/s]
DS: Default Speed 25 1.8 12.5
HS: High Speed 50 1.8 25
SDR12 25 1.8 12.5
SDR25 50 1.8 25
SDR50 100 1.8 50
SDR104 208 1.8 104
DDR50 50 1.8 50
Table 6: Supported SDIO bus speed modes