Data Sheet

JODY-W2 series - Data sheet
UBX-18017567 - R07 Pin definition Page 18 of 46
C1 - Public
Function Pin Name Pin No. Power Type Signal Name Remarks
Power VBAT 2 VBAT PWR Module supply input
Voltage supply range:
2.8 V – 5.5 V
VIO 3 VIO PWR VIO supply
Nominal supply range:
1.8 V or 3.3 V
1V8 4 1V8 PWR VIO supply for SDIO
Supply for analog part
Nominal supply: 1.8 V
GND
1, 5, 19, 20, 22,
23, 25, 27, 28, 30,
31, 49
GND GND
Exposed Pins - GND GND Connect to Ground
SDIO host
interface
SD_CLK 53 1V8 I SDIO Clock SDIO Clock input
SD_CMD 52 1V8 I/O SDIO Command SDIO command line
SD_D0 54 1V8 I/O SDIO data 0 SDIO data line bit [0]
SD_D1 55 1V8 I/O SDIO data 1 SDIO data line bit [1]
SD_D2 50 1V8 I/O SDIO data 2 SDIO data line bit [2]
SD_D3 51 1V8 I/O SDIO data 3 SDIO data line bit [3]
UART host
interface
BT_UART_TX 36 VIO O UART TX
Bluetooth UART,
connect to Host RX
BT_UART_RX 37 VIO I UART RX
Bluetooth UART,
connect to Host TX
BT_UART_RTS 38 VIO O UART RTS
Bluetooth UART,
connect to Host CTS
BT_UART_CTS 39 VIO I UART CTS
Bluetooth UART,
connect to Host RTS
PCM
interface
PCM_CLK 16 VIO I/O PCM clock
Input if slave, Output if
master
PCM_SYNC 15 VIO I/O PCM Frame Sync
Input if slave, Output if
master
PCM_IN 18 VIO I PCM data in
PCM_OUT 17 VIO O PCM data out
Configuration CONFIG[0] 7 1V8 I Configuration pin
See section 2.1 for
bootstrap
configuration
CONFIG[1] 8 1V8 I Configuration pin
See section 2.1 for
bootstrap
configuration
RESERVED
CONFIG[2]
6 1V8
Reserved for future
configuration,
A “DNI” pull-up
resistor should be
added at this pin to
respond to future
chipset changes.
Clock and
power
up/down
interface
PDn 58 1V8 PDn Wi-Fi power enable
Power-down interface
of the chipset:
0 = power-down mode
1 = normal mode
CORE_PDn 59 1V8 I CORE_PDn
Enable pin of the core
voltage regulator.
0 = power supply off
Connect with PDn