Data Sheet

JODY-W2 series - Data sheet
UBX-18017567 - R07 Interfaces Page 13 of 46
C1 - Public
Figure 7: SDIO DAT [3:0] timing diagram – DDR50 mode (50 MHz, 1.8 V)
Symbol Parameter Condition Min. Typ Max. Units
Clock
TCLK Clock time
50 MHz (max) between rising edges
DDR50 20 - - ns
tCR, tCF, Rise time, fall time
TCR, TCF < 4.00 ns (max) at 50 MHz
CCARD = 10 pF
DDR50 - - 0.2*TCLK ns
Clock Duty DDR50 45 - 55 %
CMD Input (referenced to clock rising edge)
tIS Input setup time
CCARD ≤ 10 pF (1 card)
DDR50 6 - - ns
tIH Input hold time
CCARD ≤ 10 pF (1 card)
DDR50 0.8 - - ns
CMD Output (referenced to clock rising edge)
tODLY
Output delay time during data transfer
mode CL ≤ 30 pF (1 card)
DDR50 - - 13.7 ns
tOHLD Output hold time
CL ≥ 15 pF (1 card)
DDR50 1.5 - - ns
DAT[3:0] Input (referenced to clock rising and falling edges)
tIS2x Input setup time
CCARD ≤ 10 pF (1 card)
DDR50 3 ns
tIH2x Input hold time
CCARD ≤ 10 pF (1 card)
DDR50 0.8 ns
DAT[3:0] Output (referenced to clock rising and falling edges)
tODLY2x
(max)
Output delay time during data transfer
mode CL ≤ 25 pF (1 card)
DDR50 7.0 ns
tODLY2x
(min)
Output hold time
CL ≥ 15 pF (1 card)
DDR50 1.5 ns
Table 10: SDIO timing data – DDR50 mode (50 MHz, 1.8 V)