Data Sheet

JODY-W2 series - Data sheet
UBX-18017567 - R07 Interfaces Page 12 of 46
C1 - Public
2.2.3 SDR104 mode (208 MHz, 1.8 V)
Figure 5: SDIO protocol timing diagram – SDR104 mode (208 MHz, 1.8 V)
Symbol
Parameter
Condition
Min.
Typ
Max.
Units
f
PP
Clock frequency
SDR104
0
-
208
MHz
T
IS
Input setup time
SDR104
1.4
-
-
ns
T
IH
Input hold time
SDR104
0.8
-
-
ns
T
CLK
Clock time
SDR104
4.8
-
-
ns
t
CR,
t
CF,
Rise time, fall time
T
CR
, T
CF
< 0.96 ns (max) at 208 MHz
C
CARD
= 10 pF
SDR104
-
0.2*T
CLK
ns
T
OP
Card output phase
SDR104
0
-
10
ns
T
ODW
Output timing of variable data window
SDR104
2.88
-
-
ns
Table 9: SDIO timing data – SDR104 mode (208 MHz) (1.8 V)
2.2.4 DDR50 Mode (50 MHz, 1.8 V)
Figure 6: SDIO CMD timing diagram – DDR50 mode (50 MHz, 1.8 V)