Data Sheet

JODY-W2 series - Data sheet
UBX-18017567 - R07 Interfaces Page 10 of 46
C1 - Public
2.2.1 Default speed and high speed modes (1.8 V)
Figure 2: SDIO Protocol timing diagram - default speed mode (1.8 V)
Figure 3: SDIO Protocol timing diagram – high speed mode (1.8 V)
Symbol Parameter Condition Min. Typ. Max. Units
f
PP
Clock frequency – Data
Transfer Mode
Normal 0 - 25 MHz
High speed 0 - 50 MHz
f
OD
Clock frequency –
Identification Mode
Normal 0 400 KHz
High speed 0 - 400 KHz
t
WL
Clock low time Normal 10 - - ns
High speed 7 - - ns
t
WH
Clock high time Normal 10 - - ns
High speed 7 - - ns
t
TLH
Clock rise time Normal - - 10 ns
High speed - - 3 ns
t
THL
Clock low time Normal - - 10 ns
High speed - - 3 ns
t
ISU
Input setup time Normal 5 - - ns
High speed 6 - - ns
SDIO_CLK
INPUT
OUTPUT
f
PP
t
THL
t
WL
t
WH
t
TLH
t
ODLY
(max)
t
ODLY
(min)
t
ISU
t
IH
SDIO_CLK
INPUT
OUTPUT
f
PP
t
THL
t
WL
t
WH
t
TLH
t
ODLY
t
OH
t
ISU
t
IH
50% VCC