User Manual

EMMY-W1 series - User Manual
UBX-16015271 - R03 Product Information Interfaces
Page 11 of 46
Figure 4: SDIO protocol timing diagram – High speed mode (3.3 V)
Symbol
Parameter
Condition
Min.
Typ
Max.
Units
f
PP
Clock frequency
Normal
0
-
25
MHz
High speed
0
-
50
MHz
T
WL
Clock low time
Normal
10
-
-
ns
High speed
7
-
-
ns
T
WH
Clock high time
Normal
10
-
-
ns
High speed
7
-
-
ns
T
ISU
Input setup time
Normal
5
-
-
ns
High speed
6
-
-
ns
T
IH
Input hold time
Normal
5
-
-
ns
High speed
2
-
-
ns
T
ODLY(max)
Maximal Output delay time
Normal
-
14
ns
T
ODLY(min)
Minimal Output delay time
Normal
-
0
ns
T
ODLY
Output delay time CL ≤ 40 pF
(1 card)
Normal
-
14
ns
T
OH
Output hold time
High speed
2.5
-
-
ns
Table 4: SDIO timing data – Default speed, High speed modes (3.3 V)
2.2.2 SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8 V)
Figure 5: SDIO protocol timing diagram – SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8 V)