Integration Manual
SARA-R4/N4 series - System Integration Manual
UBX-16029218 - R13 Design-in Page 87 of 119
2.14 Design-in checklist
This section provides a design-in checklist.
2.14.1 Schematic checklist
The following are the most important points for a simple schematic check:
DC supply must provide a nominal voltage at VCC pin within the operating range limits.
DC supply must be capable of supporting the highest peak / pulse current consumption values and the maximum
averaged current consumption values in connected mode, as specified in the SARA-R4/N4 series Data Sheet [1].
VCC voltage supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors, in
particular if the application device integrates an internal antenna.
Do not apply loads which might exceed the limit for maximum available current from V_INT supply.
Check that voltage level of any connected pin does not exceed the relative operating range.
Provide accessible test points directly connected to the following pins of the SARA-R4/N4 series modules: V_INT,
PWR_ON and RESET_N for diagnostic purposes.
Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.
Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if accessible.
Check UART signals direction, as the modules’ signal names follow the ITU-T V.24 Recommendation [5].
Capacitance and series resistance must be limited on each high speed line of the USB interface.
It is strongly recommended to provide accessible test points directly connected to the USB interface pins
(VUSB_DET, USB_D+ and USB_D- pins).
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ resistor on the board
in series to the GPIO when those are used to drive LEDs.
Provide adequate precautions for EMC / ESD immunity as required on the application board.
Do not apply voltage to any generic digital interface pin of SARA-R4/N4 series modules before the switch-on of
the generic digital interface supply source (V_INT).
All unused pins can be left unconnected.
2.14.2 Layout checklist
The following are the most important points for a simple layout check:
Check 50 Ω nominal characteristic impedance of the RF transmission line connected to the ANT port (antenna
RF interface).
Ensure no coupling occurs between the RF interface and noisy or sensitive signals (SIM signals, high-speed digital
lines such as USB, and other data lines).
Optimize placement for minimum length of RF line.
Check the footprint and paste mask designed for SARA-R4/N4 series module as illustrated in section 2.11.
VCC line should be enough wide and as short as possible.
Route VCC supply line away from RF line / part (refer to Figure 28) and other sensitive analog lines / parts.
The VCC bypass capacitors in the picoFarad range should be placed as close as possible to the VCC pins, in
particular if the application device integrates an internal antenna.
Ensure an optimal grounding connecting each GND pin with application board solid ground layer.
Use as many vias as possible to connect the ground planes on multilayer application board, providing a dense
line of vias at the edges of each ground area, in particular along RF and high speed lines.
Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal integrity.
USB_D+ / USB_D- traces should meet the characteristic impedance requirement (90 Ω differential and 30 Ω
common mode) and should not be routed close to any RF line / part.