Integration Manual

SARA-R4/N4 series - System Integration Manual
UBX-16029218 - R13 Design-in Page 79 of 119
2.6.5 DDC (I
2
C) interface
2.6.5.1 Guidelines for DDC (I
2
C) circuit design
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☞ DDC (I
2
C) interface is not supported by “00” and “01” product versions: the DDC (I
2
C) interface pins should not be
driven by any external device.
The DDC I
2
C-bus master interface can be used to communicate with u-blox GNSS receivers and other external I
2
C-bus
slaves as an audio codec.
The SDA and SCL pins of the module are open drain output as per I
2
C bus specifications [9], and they have internal pull-
up resistors to the V_INT 1.8 V supply rail of the module, so there is no need of additional pull-up resistors on the external
application board.
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☞ Capacitance and series resistance must be limited on the bus to match the I
2
C specifications (1.0 µs is the maximum
allowed rise time on the SCL and SDA lines): route connections as short as possible.
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☞ ESD sensitivity rating of the DDC (I
2
C) pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection
level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection
(e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.
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☞ If the pins are not used as DDC bus interface, they can be left unconnected.