Integration Manual

SARA-R4/N4 series - System Integration Manual
UBX-16029218 - R13 Design-in Page 78 of 119
Use the following general routing guidelines to minimize signal quality problems:
• Route USB_D+ / USB_D- lines as a differential pair
• Route USB_D+ / USB_D- lines as short as possible
• Ensure the differential characteristic impedance (Z
0
) is as close as possible to 90 Ω
• Ensure the common mode characteristic impedance (Z
CM
) is as close as possible to 30 Ω
• Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled differential micro-
strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear PCB area
Figure 49 and Figure 50 provide two examples of coplanar waveguide designs with differential characteristic impedance
close to 90 Ω and common mode characteristic impedance close to 30 Ω. The first transmission line can be implemented
in case of 4-layer PCB stack-up herein described, the second transmission line can be implemented in case of 2-layer PCB
stack-up herein described.
35 µm
35 µm
35 µm
35 µm
270 µm
270 µm
760 µm
L1 Copper
L3 Copper
L2 Copper
L4 Copper
FR-4 dielect ric
FR-4 dielect ric
FR-4 dielect ric
35 0 µm 40 0 µm40 0 µm350 µm40 0 µm
Figure 49: Example of USB line design, with Z
0
close to 90 Ω
ΩΩ
Ω and Z
CM
close to 30 Ω
ΩΩ
Ω, for the described 4-layer board layup
35 µm
35 µm
1510 µm
L2 Copper
L1 Copper
FR-4 dielect ric
740 µm 410 µm410 µm740 µm410 µm
Figure 50: Example of USB line design, with Z
0
close to 90 Ω
ΩΩ
Ω and Z
CM
close to 30 Ω
ΩΩ
Ω, for the described 2-layer board layup
2.6.3 SPI interface
2.6.3.1 Guidelines for SPI circuit design
☞
☞☞
☞ The SPI interface is not supported by “00”, “01”, “02” and “52” product versions: the SPI interface pins should not be
driven by any external device.
2.6.4 SDIO interface
2.6.4.1 Guidelines for SDIO circuit design
☞
☞☞
☞ The SDIO interface is not supported by “00”, “01”, “02” and “52” product versions: the SDIO interface pins should
not be driven by any external device.