Integration Manual

SARA-R4/N4 series - System Integration Manual
UBX-16029218 - R13 Design-in Page 77 of 119
2.6.2 USB interface
2.6.2.1 Guidelines for USB circuit design
The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single-ended mode for full
speed signaling handshake, as well as in differential mode for high speed signaling and data transfer.
USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as required by the USB 2.0
specification [4] are part of the module USB pins driver and do not need to be externally provided.
The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input (see the SARA-R4/N4
series Data Sheet [1]). Neither the USB interface nor the whole module is supplied by the VUSB_DET input: the VUSB_DET
senses the USB supply voltage and absorbs few microamperes.
Routing the USB pins to a connector, they will be externally accessible on the application device. According to EMC/ESD
requirements of the application, an additional ESD protection device with very low capacitance should be provided close
to accessible point on the line connected to this pin, as described in Figure 48 and Table 33.
☞
☞☞
☞ The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher
protection level could be required if the lines are externally accessible and it can be achieved by mounting a very low
capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on
the lines connected to these pins, close to accessible points.
The USB pins of the modules can be directly connected to the USB host application processor without additional ESD
protections if they are not externally accessible or according to EMC/ESD requirements.
D+
D-
GND
29
USB_D+
28
USB_D-
GND
USB DEVICE
CONNECTOR
VBUS
D+
D-
GND
29
USB_D+
28
USB_D-
GND
USB HOST
PROCESSOR
SARA-R4/ N4 SARA-R4/ N4
VBUS
17
VUSB_DET
17
VUSB_DET
D1 D2 D3
C1
C1
0Ω
Test -Point
0Ω
Test -Point
0Ω
Test -Point
Figure 48: USB Interface application circuits
Reference Description Part Number - Manufacturer
C1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata
D1, D2, D3 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics
Table 33: Components for USB application circuits
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☞☞
☞ If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external USB VBUS
supply voltage needs to be removed from the VUSB_DET input of the module to let it enter the Power Saving Mode
defined in 3GPP Rel.13.
☞
☞☞
☞ If the USB interface pins are not used, they can be left unconnected on the application board, but it is strongly
recommended to provide accessible test points directly connected to the USB interface pins (VUSB_DET, USB_D+,
USB_D-).
2.6.2.2 Guidelines for USB layout design
The USB_D+ / USB_D- lines require accurate layout design to achieve reliable signaling at the high speed data rate (up to
480 Mb/s) supported by the USB serial interface.
The characteristic impedance of the USB_D+ / USB_D- lines is specified by the Universal Serial Bus Revision 2.0
specification [4]. The most important parameter is the differential characteristic impedance applicable for the odd-mode
electromagnetic field, which should be as close as possible to 90 Ω differential. Signal integrity may be degraded if PCB
layout is not optimal, especially when the USB signaling lines are very long.