Integration Manual

SARA-R4/N4 series - System Integration Manual

UBX-16029218 - R13 Design-in Page 60 of 119

35 µm

1510 µm

L2 Copper

L1 Copper

FR-4 dielect ric

120 0 µm 40 0 µm400 µm

Figure 33: Example of 50 Ω

ΩΩ

Ω coplanar waveguide transmission line design for the described 2-layer board layup

If the two examples do not match the application PCB stack-up, then the 50 Ω characteristic impedance calculation can

be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys Corporation,

or using freeware tools like Avago / Broadcom AppCAD (https://www.broadcom.com/appcad) taking care of the

approximation formulas used by the tools for the impedance computation.

To achieve a 50 Ω characteristic impedance, the width of the transmission line must be chosen depending on:

• the thickness of the transmission line itself (e.g. 35 µm in the example of Figure 32 and Figure 33)

• the thickness of the dielectric material between the top layer (where the transmission line is routed) and the inner

closer layer implementing the ground plane (e.g. 270 µm in Figure 32, 1510 µm in Figure 33)

• the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material in Figure 32

and Figure 33)

• the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line (e.g.

500 µm in Figure 32, 400 µm in Figure 33)

If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the

track width of the micro strip, use the “Coplanar Waveguide” model for the 50 Ω calculation.

Additionally to the 50 Ω impedance, the following guidelines are recommended for transmission lines design:

• Minimize the transmission line length: the insertion loss should be minimized as much as possible, in the order of a

few tenths of a dB,

• Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of component present on the

RF transmission lines, if top-layer to buried layer dielectric thickness is below 200 µm, to reduce parasitic capacitance

to ground,

• The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible: avoid abrupt

changes of width and spacing to GND,

• Add GND stitching vias around transmission lines, as described in Figure 34,

• Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground layer, providing

enough vias on the adjacent metal layer, as described in Figure 34,

• Route RF transmission lines far from any noise source (as switching supplies and digital lines) and from any sensitive

circuit (as USB),

• Avoid stubs on the transmission lines,

• Avoid signal routing in parallel to transmission lines or crossing the transmission lines on buried metal layer,

• Do not route microstrip lines below discrete component or other mechanics placed on top layer

Two examples of a suitable RF circuit design are illustrated in Figure 34, where the antenna detection circuit is not

implemented (if the antenna detection function is required by the application, follow the guidelines for circuit and layout

implementation detailed in section 2.4.2):

• In the first example shown on the left, the ANT pin is directly connected to an SMA connector by means of a suitable

50 Ω transmission line, designed with the appropriate layout.