User's Manual

SARA-G3 and SARA-U2 series - System Integration Manual

UBX-13000995 - R18 Advance Information Design-in

Page 97 of 206

2.2.1.6 Additional guidelines for VCC supply circuit design

To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines

(connected to the VCC and GND pins of the module) on the application board and battery pack should also be

considered and minimized: cabling and routing must be as short as possible to minimize power losses.

Three pins are allocated for VCC supply. Another twenty pins are designated for GND connection. It is highly

recommended to properly connect all the VCC pins and all the GND pins to supply the module, to minimize

series resistance losses.

To avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a single-slot 2G

voice/data call (when current consumption on the VCC supply can rise up to the maximum peak / pulse current

specified in the SARA-G3 series Data Sheet [1] or in the SARA-U2 series Data Sheet [2]), place a bypass capacitor

with large capacitance (more than 100 μF) and low ESR near the VCC pins, for example:

x 330 μF capacitance, 45 m: ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor)

The use of very large capacitors (i.e. greater then 1000 μF) on the VCC line should be carefully evaluated, since

the voltage at the VCC pins voltage must ramp from 2.5 V to 3.2 V in less than 1 ms to switch on the SARA-U2

modules or in less than 4 ms to switch on the SARA-G3 modules by applying VCC supply, that otherwise can be

switched on by forcing a low level on the RESET_N pin during the VCC rising edge and then releasing the

RESET_N pin when the VCC supply voltage stabilizes at its proper nominal value.

To reduce voltage ripple and noise, especially if the application device integrates an internal antenna, place the

following bypass capacitors near the VCC pins:

x 100 nF capacitor (e.g Murata GRM155R61C104K) to filter digital logic noise from clocks and data sources

x 10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources

x 56 pF capacitor with Self-Resonant Frequency in 800/900 MHz range (e.g. Murata GRM1555C1E560J) to

filter transmission EMI in the GSM/EGSM bands

x 15 pF capacitor with Self-Resonant Frequency in 1800/1900 MHz range (e.g. Murata GRM1555C1E150J) to

filter transmission EMI in the DCS/PCS bands

A series ferrite bead for GHz band noise can be placed close to the

VCC pins of the module for additional noise

filtering, but in general it is not strictly required, with the exception of SARA-U201 modules.

On SARA-U201 modules add the following component as close as possible to the VCC pins:

x Ferrite bead for GHz band noise (e.g. Murata BLM18EG221SN1) implementing the circuit described in Figure

45 to filter out EMI in all the GSM / UMTS bands.

For devices integrating an internal antenna, it is recommended to provide space to allocate all the

components shown in Figure 44 or Figure 45 and listed in Table 27. The mounting of each single

component depends on the specific application design.

GND

C3 C2

SARA-G3 / SARA-U2

(except SARA-U201)

VCC

3V8

Figure 44: Suggested schematic and layout design for SARA-G3 and SARA-U2 series (except for the SARA-U201 module): the

VCC bypass capacitors are used to reduce ripple / noise on VCC voltage profile and to avoid undershoot / overshoot on VCC

voltage drops