Specifications

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Enable the DRAM controller to read/write ECC check-bits on the DIMMs and it
allows the north bridge to check and correct ECC errors on the DRAM bus during
normal CPU or bus master read requests.
Options: Disabled / Enabled
ECC Error Log
Enable the MCA to log or report ECC errors on the DRAM bus.
NOTE: The MCA must still be programmed according to the desired MCE outcome.
Options: Disabled / Enabled
Chipkill
Enable 4-bit ECC mode<Chipkill> on dram controllers with all x4 ECC capable
DIMMs. Setting to Auto will enable 4-bit ECC mode only when memory is
configured for 128-bit operations.
Options: Disabled / Enabled
ECC Scrub Redirection
Enable the northbridge to force a write to DRAM with corrected data when a
correctable error on the DRAM bus is detected during a normal CPU or bus master
read request.
Options: Disabled / Enabled
DRAM ECC Scrub Control
Sets the rate of background scrubbing for DRAM.
Options: Disabled / Enabled
DCache ECC Scrub Control
Sets the rate of background scrubbing for the DCache.
Options: Disabled / Enabled
L2 ECC Scrub Control
Sets the rate of background scrubbing for the L2 cache.
Options: Disabled / Enabled
ECC Multibit Error Detection
Enable multibit ECC error detection.
Options: Disabled / Enabled