User Manual

74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 28 June 2013 3 of 18
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20 and
DHXQFN20
74LVC245A
74LVCH245A
DIR V
CC
A0 OE
A1 B0
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
GND B7
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1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
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74LVC245A
74LVCH245A
Transparent top view
B6
A6
A7
B5
A5 B4
A4 B3
A3 B2
A2 B1
A1 B0
A0 OE
GND
B7
DIR V
CC
9
12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10 11
1
20
terminal 1
index area
GND
(1)
Table 2. Pin description
Symbol Pin Description
DIR 1 direction control
A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input/output
GND 10 ground (0 V)
B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input/output
OE
19 output enable input (active LOW)
V
CC
20 supply voltage