Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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6.4.12.6 MII Management PDI Access State (0x0517)
Bit Description ECAT PDI Reset Value
0 Access to MII management:
0: ECAT has access to MII management
1: PDI has access to MII management
r/- r/(w)
1 Force PDI Access State:
0: Do not change Bit 0x0517.0
1: Reset Bit 0x0517.0 to 0
r/w r/-
7:2 Reserved, write 0 r/- r/-
Table 69: Register 0x0517 (MI PDI State)
6.4.12.7 PHY Port Status (0x0518:0x051B)
Bit Description ECAT PDI Reset Value
0 Physical link status (PHY status register 1.2):
0: No physical link / 1: Physical link detected
r/- r/-
1 Link status (100 Mbit/s, Full Duplex, Autonego-
tiation):
0: No link / 1: Link detected
r/- r/-
2 Link status error:
0: No error
1: Link error, link inhibited
r/- r/-
3 Read error:
0: No read error occurred
1: A read error has occurred
Cleared by writing any value to at least one of
the PHY Status Port registers.
r/
(w/clr)
r/
(w/clr)
4 Link partner error:
0: No error detected / 1: Link partner error
r/- r/-
5 PHY configuration updated:
0: No update
1: PHY configuration was updated
Cleared by writing any value to at least one of
the PHY Status Port registers.
r/
(w/clr)
r/
(w/clr)
31:0 Reserved r/- r/-
Table 70: Register 0x0518+y (PHY Port Status)
Note
r/(w): write access depends on assignment of MI (ECAT/PDI).
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