Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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6.4.12 MII Management Interface
Address Length
(Byte)
Description
MII Management Interface
0x0510:0x0511 2 MII Management Control/Status
0x0512 1 PHY Address
0x0513 1 PHY Register Address
0x0514:0x0515 2 PHY Data
0x0516 1 MII Management ECAT Access State
0x0517 1 MII Management PDI Access State
0x0518:0x051B 4 PHY Port Status
Table 63: MII Management Interface Register Overview
6.4.12.1 MII Management Control/Status (0x0510:0x0511)
Bit Description ECAT PDI Reset Value
0 Write enable*:
0: Write disabled
1: Write enabled
This bit is always 1 if PDI has MI control.
r/(w) r/-
1 Management Interface can be controlled by
PDI (registers 0x0516:0x0517):
0: Only ECAT control
1: PDI control possible
r/- r/-
2 MI link detection (link configuration, link detec-
tion, registers 0x0518:0x051B):
0: Not available
1: MI link detection active
r/- r/-
7:3 PHY address of port 0 r/- r/-
9:8 Command register*:
Write: Initiate command.
Read: Currently executed command
Commands:
00: No command/MI idle (clear error bits)
01: Read
10: Write
Others: Reserved/invalid commands (do not
issue)
r/(w) r/(w)
12:10 Reserved, write 0 r/- r/-
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