Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
79 / 204
Bit Description ECAT PDI Reset Value
14 Error Write Enable
∗2
:
0: No error
1: Write Command without Write enable
r/- r/-
15 Busy:
0: EEPROM Interface is idle
1: EEPROM Interface is busy
r/- r/-
Table 59: Register 0x0502:0x0503 (PROM Cntrl)
Note
r/(w): write access depends upon the assignment of the EEPROM interface
(ECAT/PDI). Write access is generally blocked if EEPROM interface is busy
(0x0502.15=1).
Note
r/[w]: EEPROM emulation only: write access is possible if EEPROM interface is
busy ( 0x0502.15 =1). PDI acknowledges pending commands by writing a 1 into
the corresponding command register bits (0x0502.10:8).
Errors can be indicated by writing a 1 into the error bit 0x0502.13 . Acknowledging
clears AL Event Request 0x0220.5.
*1 Write Enable bit 0 is self-clearing at the SOF of the next frame, Command bits [10:8] are self-clearing
after the command is executed (EEPROM Busy ends). Writing "‘000"’ to the command register will also clear
the error bits [14:13]. Command bits [10:8] are ignored if Error Acknowledge/Command is pending (bit 13).
*2 Error bits are cleared by writing "‘000"’ (or any valid command) to Command Register Bits [10:8].
6.4.10.4 EEPROM Address (0x0504:0x0507)
Bit Description ECAT PDI Reset Value
31:0 EEPROM Address
0: First word (= 16 bit)
1: Second word
. . .
Actually used EEPROM Address bits:
[9:0]: EEPROM size up to 16 kBit
[17:0]: EEPROM size 32 kBit . . . 4 Mbit
[32:0]: EEPROM Emulation
r/(w) r/(w)
Table 60: Register 0x0504:0x0507 (PROM Address)
Note
r/(w): write access depends upon the assignment of the EEPROM interface
(ECAT/PDI). Write access is generally blocked if EEPROM interface is busy
(0x0502.15=1).
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