Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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6.4.6.4 PDI SPI Slave Configuration (0x0150)
The PDI configuration register 0x0150 and the extended PDI configuration registers 0x0152:0x0153 depend
on the selected PDI. The Sync/Latch[1:0] PDI configuration register 0x0151 is independent of the selected
PDI. The TMC8460, TMC8461, TMC8462, and TMC8670 devices support SPI Slave PDI only.
Bit Description ECAT PDI Reset Value
1:0 SPI mode:
00: SPI mode 0
01: SPI mode 1
10: SPI mode 2
11: SPI mode 3
NOTE: SPI mode 3 is recommended for Slave
Sample Code
NOTE: SPI status flag is not available in SPI
modes 0 and 2 with normal data out sample.
r/- r/-
3:2 SPI_IRQ output driver/polarity:
00: Push-Pull active low
01: Open Drain (active low)
10: Push-Pull active high
11: Open Source (active high)
r/- r/-
4 SPI_CSNL polarity:
0: Active low
1: Active high
r/- r/-
5 Data Out sample mode:
0: Normal sample (SPI_MISO and SPI_MOSI are
sampled at the same SPI_CLK edge)
1: Late sample (SPI_MISO and SPI_MOSI are
sampled at different SPI_CLK edges)
r/- r/-
7:6 Reserved, set EEPROM value 0 r/- r/-
Table 37: Register 0x0150 (PDI SPI CFG)
6.4.6.5 SYNC/LATCH Configuration (0x0151)
Bit Description ECAT PDI Reset Value
1:0 SYNC0 output driver/polarity:
00: Push-Pull active low
01: Open Drain (active low)
10: Push-Pull active high
11: Open Source (active high)
r/- r/- TMC8461: 10
TMC8462: 10
2 SYNC0/LATCH0 configuration:
0: LATCH0 Input
1: SYNC0 Output
r/- r/- TMC8461: 1
TMC8462: 1
3 SYNC0 mapped to AL Event Request register
0x0220.2:
0: Disabled
1: Enabled
r/- r/- TMC8461, TMC8462: de-
pends on configuration
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