Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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6.2 Overview of Available Chip Features
The following table shows EtherCAT chip features available in TRINAMIC’s EtherCAT slave controller solu-
tions.
Chip Feature / Description Domain TMC8460 TMC8461 TMC8462 TMC8670
Extended DL control register 0x0102:0x0103 enabled Register 1 1 1 1
AL Status code register 0x0134:0x0135 enabled Register 1 1 1 1
ECAT interrupt mask 0x0200:0x0201 enabled Register 1 1 1 1
Configured station alias 0x0012:0x0013 enabled Register 1 1 1 1
General purpose inputs 0x0F18:0x0F1F enabled Register 0 0 0 0
General purpose outputs 0x0F10:0x0F17 enabled Register 0 0 0 0
AL event mask 0x0204:0x0207 enabled Register 1 1 1 1
Physical RD/WR offset 0x0108:0x0109 enabled Register 0 1 1 0
Bridge port PDI (0x07) enabled Register 0 0 0 0
Writable Watchdog divider 0x0400:0x0401 and Watchdog PDI
0x0410:0x0411 enabled
Watchdog 1 1 1 0
Watchdog counters 0x0442:0x0444 enabled Watchdog 1 1 1 1
ECAT write protection 0x0020:0x0031 enabled Ext. Function 0 1 1 0
Reset registers 0x0040:0x0041 enabled Ext. Function 1 1 1 1
FPGA update at 0x0E00 enabled Ext. Function 0 0 0 0
DC Sync event times enabled Ext. Function 1 1 1 0
ECAT processing unit and PDI error counters/PDI error code
0x030C:0x030E enabled
Ext. Function 1 1 1 0
User RAM disabled Ext. Functions 1 0 0 0
1: POR Values, 0: VENDOR ID Ext. Functions 0 0 0 0
EEPROM control by PDI enabled PHY Layer 0 0 0 0
Lost link counters 0x0310:0x0313 enabled PHY layer 1 1 1 0
MII management interface 0x0510 enabled PHY layer 1 1 1 1
Enhanced link detection for MII enabled PHY layer 1 1 1 1
Link detection and configuration for MII enabled PHY layer 0 1 1 0
PDI support for MII management interface enabled PHY layer 1 1 1 1
Automatic MII TX shift enabled PHY layer 1 1 1 1
Extended RX Error counter registers 0x0314:0x0317 and
0x0320:0x0327 enabled
PHY layer 0 0 0 0
RUN LED enabled LEDs 1 1 1 1
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