Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
30 / 204
5.3 Ethernet Physical Layer Connection
TMC8462 comes with two integrated 100-Mbit Ethernet PHYs eliminating the need for external PHY
components. The physical media interface can connect to (shielded) twisted pair copper buses ((S)TPC).
Port signals with index 0 represent the EtherCAT IN port. Port signals with index 1 represent the EtherCAT
OUT port.
Figure 17: Physical bus interface pins
TMC8462 pin Description
TNx Negative pin of differential transmit output pair
TPx Positive pin of differential transmit output pair
RNx Negative pin of differential receive output pair
RPx Positive pin of differential receive output pair
REGOUTx This is a regulator power output. A 10uF and 0.1uF should be connected to
this pin for filtering power noise.
MCLK PHY configuration clock output
MDIO PHY configuration data in-/output
Table 6: Physical bus interface pin description
©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany
Terms of delivery and rights to technical change reserved.
Download newest version at www.trinamic.com