Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21

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Watchdog Register Set

Once initialized, the watchdog timer monitors the application for activity and

allows setting of pre-programmed I/O patterns, in case the time limit is expired without activity.

In order to allow tuning of this time limit, the maximum time between two trigger events becomes

measured. This function also allows delay time measurement for input channels (i.e. when no watchdog

action is chosen). The watchdog timeout counter starts from zero up to WD_TIME. When it reaches

WD_TIME, it triggers the watchdog action.

The selected watchdog event resets the timeout counter. As trigger sources, the internal EtherCAT start

of frame (PDI_SOF), the two SPI chip select signals (PDI_SPI_CSN and MFC_CTRL_SPI_CSN) as well as any

combination of I/O lines can be used. For the I/O lines (MFCIO00 to MFCIO23), the polarity and edge are

programmable.

When using an MFCIOxx pin programmed as output and as watchdog trigger, the watchdog circuitry will

monitor the real output by checking the polarity of the output signal. This way, also a short circuit condition

will be detected. The chip select signals respond to a rising edge (i.e. when the SPI interface loads the SPI

shift register data into the corresponding registers).

Figure 50: Structure of the MFC IO watchdog unit

Watchdog Output Port Conﬁguration

The following table contains the assignments of ports/signals

to the conﬁguration bits in the WD_OUT_MASK_POL register. An MFCIOxx pin programmed as output is

called MFCOxx.

Bit # Signal Bit # Signal

0 MFCO00 polarity 32 MFCO00 mask

1 MFCO01 polarity 33 MFCO01 mask

2 MFCO02 polarity 34 MFCO02 mask

3 MFCO03 polarity 35 MFCO03 mask

4 MFCO04 polarity 36 MFCO04 mask

5 MFCO05 polarity 37 MFCO05 mask

6 MFCO06 polarity 38 MFCO06 mask

7 MFCO07 polarity 39 MFCO07 mask

8 MFCO08 polarity 40 MFCO08 mask

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