Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
172 / 204
7.15 MFC IO PWM Block
The MFC IO block of TMC8462 offers a 4-channel pulse width modulation (PWM) block including a pro-
grammable brake before make (BBM) unit and selection of different PWM modes.
Both high side and low side control signals are available as separate outputs. A single PWM counter gener-
ates the four synchronous PWM signals. The configurable maximum count defines the PWM frequency.
Left aligned PWM, centered PWM, and right aligned PWM is selectable. The BBM timing is individually
programmable for high side and low side. Fixed pulses are available for triggering of ADCs or triggering
interrupts of a CPU. Additional programmable trigger output signals are available. Signal PULSE_ZERO
indicates a start of a new PWM cycle and PULSE_CENTER the center of a PWM cycle. Both are fixed.
The two programmable signals PULSE_A and PULSE_B are for advanced ADC triggering. The signal
PULSE_AB is the logical or of PULSE_A and PULSE_B.
The polarities of the high side, low side, and trigger signals of the PWM unit are programmable.
Figure 39: Block structure of the MFC IO PWM Block
Parameter Value Description / Function Comment
f
CLK
[Hz] 100 MHz clock frequency of PWM unit f
CLK
= 1/t
CLK
t
CLK
[s] 10 ns clock period length t
CLK
= 1/f
CLK
max. t
P W M
[s] 40.96 us Length of PWM period
tP W M = t
CLK
∗ (1+ P W M_M AXCNT )
Maximum t
P W M
with maxi-
mum PWM resolution of 12
bit.
min. f
P W M
[Hz]
24.414 kHz PWM frequency = 1/t
P W M
Minimal PWM frequency
with maximum PWM resolu-
tion of 12 bit.
t
P U LSE_LEN GT H
Length of trigger pulses with
t
P U LSE_LEN GT H
= P ULSE_LEN GT H ∗
t
CLK
pulse length is adjustable
t
CLK
= 10ns
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