Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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Step Rate Accumulation Constant Register SD_CHx_STEPRATE The step direction accumulation con-
stant determines the time t
ST EP
between two successive step pulses – this is actually the step rate. Each
internal PWM clock accumulates an accumulator according to a = a + c with the accumulator constant c .
Toggle of the MSB of the accumulator register a triggers a step pulse. With this principle, the step frequency
is smarter adjustable compared to a simple frequency divider. Writing c = 0 clears the accumulator and
stops the step pulse generation. The step pulse frequency calculates as f
ST EP
= (f
CLK
/2
32
) ∗ c.
Step Counter Register SD_CHx_STEPCOUNT The step counter counts the number of steps, taking the
direction into account. This is a read only register. To reset this counter to zero set bit 4 in the SD_CFG
register.
Step Target Register SD_CHx_STEPTARGET The step target defines the number of steps to be made
when in target mode. See SD_CFG register bit 2. This register can be overwritten at any time. When the
number of steps has been made, the unit stops generating S/D pulses. When read, it gives the remaining
numbers that must still be made.
Step Compare Register SD_CHx_COMPARE This register holds a compare value in numbers of step
pulses.
Next Step Rate Register SD_CHx_NEXTSR The next step rate register contains a value of the same for-
mat as the step rate register. This value is automatically written into the step rate register SD_CHx_STEPRATE
after a successful compare of the step compare value SD_CHx_COMPARE and the actual step counter
SD_CHx_STEPCOUNT. This way, simple motion profiles can be realized.
Step Length Register SD_STEPLENGTH The duration of the step pulse – the step length – signal is
programmable for adaption to external power stages.
Note
Maximum step length: The step pulse length t
ST EP _P ULSE
must be lower than
the time t
ST EP
between step pulses to actually see step pulses at the outputs.
The condition t
ST EP _P ULSE
< t
ST EP
must be ensured by the application.
Step-to-Direction Delay Register SD_DELAY The delay between the first step pulse after a change of
the direction is programmable for adaption to external power stages to take external delay paths into
account.
Step Direction Unit Configuration Register SD_CFG The step direction configuration defines the mode
of operation (continuous or defined number of step pulses), polarity of step pulse signal and direction
signal. One bit is for zeroing of step pulse counter. One bit is for enabling and disabling of the step pulse
unit and compare mode.
Interrupt Output Signal An IRQ signal TARGET_REACHED of a single clock pulse length indicates that a
certain target position has been reached reached in terms of step counts.
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