Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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Figure 38: Step & Direction Signal Timing
Parameter Value Description / Function Comment
f
CLK
[Hz] 25 MHz clock frequency of step direction unit clock frequency of the step
direction unit
t
CLK
[s] 40 ns clock period length t
CLK
= 1/f
CLK
f
ST EP
[Hz] f
ST EP
=
(f
CLK
/2
32
) ∗ (SD_CHx_ST EP RAT E)
step frequency, pro-
grammed via step rate
accumulation constant
SD_CHx_STEPRATE
Max. f
ST EP
[Hz]
12.5 MHz Theoretical maximum value
for f
ST EP
. Usable step fre-
quency depends on step
pulse length configuration.
t
ST EP
[s] t
ST EP
= 1/f
ST EP
time between steps
t
ST EP _P ULSE
[s]
t
ST EP _P ULSE
=
(SD_ST EP _LEN GT H + 1)/f
CLK
step pulse length must be
lower than time between
step pulses!
t
ST EP _P ULSE
< t
ST EP
DIR DIR = 0 –> positive direction,
DIR = 1 –> negative direction,
direction is depending on sign of step rate
register SD_CHx_STEPRATE where the step
rate register is 2th complement
direction signal, depending
of step rate (SR) parameter,
DIR = 0 if SR > 0 or SR = 0,
DIR = 1 if SR < 0
t
ST EP 1st
[s] time to 1st step pulse since WR=0 with
t
ST EP 1st
=
2
32
/SD_CHx_ST EP RAT E ∗ t
CLK
+(SD_DELAY + 1) ∗ t
CLK
+ (2 ∗ t
CLK
)
Time between write until
the first step pulse occurs
t
ST EP 1stW R
[s]
time to first step pulse since WR=0 step delay
plus 1 internal clock plus 2 clock cycles to
pulse length
Internal processing adds an
delay
Table 203: Step and direction unit parameters
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