Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21

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Status bit Description

7 Error Flag

6 Not Acknowledge received/sent

5 Acknowledge received/sent

4 Write to slave mode

3 Read from Slave mode

2 Transmit Address mode

1 Repeated Start condition sent

0 Start condition sent

Table 200: I2C status register bits

Bits 0 and 1 are set after command 0x20 was successfully executed, either if the I2C bus was idle or a start

condition already has been sent.

A combination of Bits 2 to 6 indicates completion of an address or data cycle.

Bit 7 indicates an error during transmission. A stop condition should be sent to return to the idle state.

Status byte Status

0x00 Idle

0x01 Start sent

0x02 Repeated Start sent

0x34 Write Address ACK

0x2C Read Address ACK

0x54 Write Address NACK

0x4C Read Address NACK

0xE4 Address Error

0x48 Read Data ACK sent

0x28 Read Data NACK sent

0x30 Write Data ACK

0x50 Write Data NACK

0xF0 Write Data Error

0xFF General Error

Table 201: I2C status overview

I2C_ADDR – Address register with R/nW bit

This register contains the 7 bit address of the I2C slave and the single R(ead)/n(ot)W(rite) bit.

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