Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21

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7.12 MFC IO SPI Master Block

The SPI Master Unit provides an interface for up to four SPI slaves with a theoretically unlimited datagram

length using multiple accesses.

Figure 35: Block structure of SPI Master Unit

The basic conﬁguration requires setting the SPI frequency/bit length, the datagram length and the SPI

mode (clock polarity and phase). Extended settings are a special start-of-transmission trigger linked to the

PWM unit, the bit order, selection of one of the four SPI slaves and datagram length extension.

SPI_RX_DATA – Received Data This register contains the received datagram after an SPI transfer.

For SPI transfers with less than 64 bit, the upper bits of this register are unused.

SPI_TX_DATA – Data to transmit

The data to be sent is written to this register. Unless conﬁgured diﬀer-

ently in SPI_CONF Bits 10..8, writing to this register starts the SPI transfer.

For SPI transfers with less than 64 bit, the upper bits of this register are unused.

SPI_CONF – SPI block conﬁguration

• Bit 15 is the trigger bit that can be selected as transmission start trigger (see below).

•

Bits 10..8 allow a conﬁguration when the data transmission should start, they are interpreted as a 3

bit number:

–

In the reset conﬁguration 0, the transmission always starts when data is written to the SPI_TX

–

The settings 1 to 5 link the start of the transmission to the PWM unit, allowing synchronization

between the PWM cycle and for example a SPI ADC for current measurement. The trigger

sources are the ﬁve PWM_PULSE signals that are also available on the MFCIO crossbar. Please

refer to Section 7.15 for details about these pulses.

–

Setting 7 is a single shot trigger that starts only one transmission when Bit 15 of SPI_CONF is

written to 1.

•

Bit 6 and 5 deﬁne the clock polarity and phase of the SPI signals which deﬁne what the idle state of

the SCK signal is and when output data is changed and when input data is sampled.

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