Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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7.9 SII EEPROM MFC IO Register Configuration
All MFC registers are accessible via the MFC IO Control SPI Interface. Alternatively they can be mapped into
the ESC’s Process Data RAM to allow access via EtherCAT. In this case the mapped registers can only be
written by the EtherCAT master. But they can still be read via MFC IO Control SPI Interface.
The transfer of all enabled registers is performed in one access. To enable the data update at certain
times only, a shadow register is used for every MFC register. The exact point in time when the actual data
transfer occurs (from the shadow register into a write register or from a read register into the shadow
register) is based on the chosen trigger source.
There is one configuration byte in the SII EEPROM (and ESC Parameter RAM respectively) for each MFC
block register. The configuration for all registers has the same options:
Bit Description
3:0 Trigger Source
4 Enable RAM transfer
0 : disabled, register access only from MCU via MFC CTRL SPI
1 : enabled, read and write access via EtherCAT, readable by MCU via MFC CTRL SPI
7:5 Unused
Table 196: Register configuration byte
Trigger
Source hex.
Trigger Source Name Description
0
h
Trigger always shadow register is transparent
1
h
SYNC0 signal distributed clocks sync pulse 0 (0->1)
2
h
SYNC1 signal distributed clocks sync pulse 1 (0->1)
3
h
LATCH0 signal distributed clocks latch input 0 (0->1)
4
h
LATCH1 signal distributed clocks latch input 1 (0->1)
5
h
EtherCAT start of frame (SOF) Start of frame on EtherCAT bus
6
h
EtherCAT end of frame (EOF) End of frame on EtherCAT bus
7
h
PDI SPI nCS=0 (Chip Select) Falling edge on PDI_SPI_CSN pin
8
h
PDI SPI nCS=1 (Chip Deselect) Rising edge on PDI_SPI_CSN pin
9
h
MFC SPI nCS=0 (Chip Select) Falling edge on MFC_CTRL_SPI_CSN pin
A
h
MFC SPI nCS=1 (Chip Deselect) Rising edge on MFC_CTRL_SPI_CSN pin
B
h
Trigger before register is handled Before data is copied to/from RAM by Memory Bridge
C
h
Trigger after register was handled After data is copied to/from RAM by Memory Bridge
D
h
Trigger on PWM counter = 0 Transfer at the zero pulse of the MFC PWM unit
E
h
Trigger never no data is transferred, can be used for debugging
F
h
Trigger always shadow register is transparent
Table 197: Trigger source descriptions
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