Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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7.8 SII EEPROM MFC IO Memory Block Mapping
The MFC registers can be mapped to specific memory areas to allow EtherCAT access, so that the data is
directly copied between each register and the assigned memory location. This allows the operation with a
less powerful application processor or even without an application processor at all in Device Emulation
mode.
The registers are dynamically mapped to one of two memory blocks:
• Memory Block 0 is used for write-registers (data direction: EtherCAT master -> MFC register)
• Memory Block 1 is used for read-registers (data direction: MFC register -> EtherCAT master).
The start address of each memory block can be configured to be anywhere in the process data RAM (1000
h
to (4FFF
h
-blocksize)).
The length of each block depends on the selected registers that are mapped into the block. Extra care
should be taken that the blocks do not overlap each other, that they do not overlap with other process
data in the DPRAM, and that the memory blocks’ start addresses are not too close at 4FFF
h
.
Memory Block 0 base address 059F
h
:059E
h
(SII EEPROM: 00A3
h
:00A2
h
)
The start address of the block that all write registers of the MFC are mapped into.
Address 059F
h
contains the upper byte of the start address. Allowed values: 10
h
...4F
h
Address 059E
h
contains the lower byte of the start address. Allowed values: 00
h
...FF
h
Memory Block 1 base address 05A1
h
:05A0
h
(SII EEPROM: 00A5
h
:00A4
h
)
The start address of the block that all read registers of the MFC are mapped into.
Address 059F
h
contains the upper byte of the start address. Allowed values: 10
h
...4F
h
Address 059E
h
contains the lower byte of the start address. Allowed values: 00
h
...FF
h
When a register is mapped to the RAM for EtherCAT transfer, its memory address depends on the other
enabled registers with a lower register number.
The start address of any enabled register will be a multiple of 4 bytes from the start address of the memory
block. Between registers that are not a multiple of 4 bytes, a padding gap is left that is not transferred.
For example if a 2 byte register, a 8 byte register a 1 byte register and a 4 byte register are enabled in a
memory block starting at 2000
h
, the memory is used as shown in this table:
Register End Address Start Address
Reg. 1 (2 byte) 2001
h
2000
h
Padding 2003
h
2002
h
Reg. 2 (8 byte) 200B
h
2004
h
Reg. 3 (1 byte) 200C
h
200C
h
Padding 200F
h
200D
h
Reg. 4 (4 byte) 2013
h
2010
h
Table 195: Register mapping example
For the actual register sizes please refer to Table 124 in Section 7.2.
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