Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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7.5 SII EEPROM MFC IO Crossbar Mapping
The TMC8462 contains a full crossbar.
The 24 MFC IO pins (16x Low Voltage 3.3V MFC IO pins and 8x High Voltage MFC IO pins) of the TMC8462
can be freely assigned to any signal coming from or going to the MFC IO functional blocks.
Without initialization from the SII EEPROM on power up or later via PDI SPI/ECAT memory access during
operation, all IOs are tri-stated.
Note
Certain output signals (e.g. PWM signals, DAC, ...) generate very short pulses
(down to 10ns) which are faster than the slew rate of the HVIO output drivers.
It is still possible to use this configuration, so that the user can evaluate if the
application specific conditions allow to work directly with the HVIO outputs.
Otherwise external signal conditioning is required.
One output signal can be mapped to multiple IO pins, for example to combine the driver strength of
multiple pins. The configuration also allows a mapping of multiple pins to one input signal, but usually
there is no reason for this configuration. When multiple pins are mapped to the same input signal, a logical
OR operation is applied to all input pins.
Each IO pin has a dedicated configuration byte in the SII EEPROM and in the ESC’s memory space within
the ESC Parameter RAM to select the functional MFC IO block signal connected to the physical IO pin:
• MFCIO00 to MFCIO15: SII EEPROM 0084
h
to 0093
h
/ ESC Parameter RAM from 0580
h
to 058F
h
• MFC_HV0 to MFC_HV7
2
: SII EEPROM: 0094
h
to 009B
h
/ ESC Parameter RAM from 0590
h
to 0597
h
An overview over all configurable MFC IO block signals is given in Table 190.
Name Function block Description Direction Value dec. Value
hex.
ZERO none Disabled - 0 00
h
LOW none Static LOW output output 1 01
h
HGH none Static HIGH output output 2 02
h
TRI none Static tristate (Z) output - 3 03
h
A ABN decoder ABN_A signal input 4 04
h
An ABN decoder ABN_An signal (for differential inputs) input 5 05
h
B ABN decoder ABN_B signal input 6 06
h
Bn ABN decoder ABN_Bn signal (for differential inputs) input 7 07
h
N ABN decoder ABN_N signal input 8 08
h
Nn ABN decoder ABN_Nn signal (for differential inputs) input 9 09
h
SCK SPI SPI SCK signal output 10 0A
h
SDI SPI SPI SDI signal input 11 0B
h
SDO SPI SPI SDO signal output 12 0C
h
CS0 SPI SPI CS0 signal output 13 0D
h
2
MFC_HV0 to MFC_HV7 ≡ MFCIO16 to MFCIO23
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