Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21

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7.3.9.5 Register 57 – WD_IN_MASK_POL

Bit Description ECAT PDI Range [Unit]

23:0 WD_IN_POL,

Input signal levels for watchdog re-triggering.

Each bit corresponds to one input line.

The polarity describes the input level for signals

selected by WD_IN_MASK required to re-trigger

the watchdog timer.

-/w -/w

31:24 unused/reserved -/- -/-

55:32 WD_IN_MASK,

Each bit corresponds to one input line.

0 = Input is not selected

1 = Input I/O[i] must reach polarity

WD_IN_POL[i] to re-trigger the watchdog

timer.

-/w -/w

63:56 unused/reserved -/- -/-

Table 182: MFC IO Register 57 – WD_IN_MASK_POL

Note

See Section 7.19 for the detailed signal mapping of WD_IN_MASK_POL.

7.3.9.6 Register 58 – WD_MAX

Bit Description ECAT PDI Range [Unit]

31:0

Peak value reached by watchdog timeout

counter.

Reset to 0 by writing to WD_TIME.

r/- r/- 0 . . . + (2

) − 1

Table 183: MFC IO Register 58 – WD_MAX

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