Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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7.3.9 Watchdog
7.3.9.1 Register 53 – WD_TIME
Bit Description ECAT PDI Range [Unit]
31:0 Watchdog time 32 bit/unsigned
0 = Watchdog off,
> 0 = number of 25MHz clock cycles
-/w -/w 0 . . . + (2
32
) − 1
Table 178: MFC IO Register 53 – WD_TIME
7.3.9.2 Register 54 – WD_CFG
Bit Description ECAT PDI Range [Unit]
0 cfg_persistent
0 = The watchdog action ends when the next
trigger event occurs
1 = A timeout situation can only be cleared by
rewriting WD_TIME
-/w -/w
1 cfg_pdi_csn_enable
1 = Retrigger by positive edge on PDI_SPI_CSN
-/w -/w
2 cfg_mfc_csn_enable
1 = Retrigger by positive edge on
MFC_CTRL_SPI_CSN
-/w -/w
3 cfg_sof_enable
1 = Retrigger by ETHERCAT start of frame
-/w -/w
4 cfg_in_edge
0 = Retrigger by input condition becoming false
1 = Retrigger by input condition becoming true
-/w -/w
6:5 unused/reserved -/- -/-
7 cfg_wd_active
1 = Signals an active watchdog timeout
-/w -/w
Table 179: MFC IO Register 54 – WD_CFG
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