Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21

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7.3.8 IRQ Control Block

7.3.8.1 Register 51 – MFCIO_IRQ_CFG

Bit Description ECAT PDI Range [Unit]

0 ABN encoder unit N-channel event -/w -/w

1 SD_CH0 target reached event -/w -/w

2 SD_CH1 target reached event -/w -/w

3 SD_CH2 target reached event -/w -/w

4 SD_CH0 compare value event -/w -/w

5 SD_CH1 compare value event -/w -/w

6 SD_CH2 compare value event -/w -/w

7 SPI new data available event -/w -/w

8 I2C new data available event -/w -/w

9 I2C transmit complete event -/w -/w

I2C new data available event OR I2C transmit

complete event

-/w -/w

11 Watchdog Timeout event -/w -/w

12 PWM zero pulse event -/w -/w

13 PWM center pulse event -/w -/w

14 PWM A pulse event -/w -/w

15 PWM B pulse event -/w -/w

16 HV_OT_FLAG has been set -/w -/w

17 BVOUT_OT_FLAG has been set -/w -/w

18 BVOUT_SC_FL has been set -/w -/w

19 B3V3_SC_FLAG has been set -/w -/w

22:20 unused/reserved -/w -/w

23 emergency input pin MFC_NES event -/w -/w

Table 176: MFC IO Register 51 – MFCIO_IRQ_CFG

Note

This register is used for masking / enabling the diﬀerent IRQ sources, which are

or-ed together to set the common MFCIO_IRQ output signal. The MFCIO_IRQ is a

dedicated package pin of TMC8462, which can be connected to a local application

controller.

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