Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21

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7.3.4.18 Register 35 – SD_CFG

Bit Description ECAT PDI

0 0/1: 0 = enabled, 1 = disabled SD_CH0 -/w -/w

1 0 = generate N pulses based on SD_CH0_STEPTARGET register value

1 = continuous mode

-/w -/w

2 S0 and S0n step pulse signal polarity -/w -/w

3 D0 and D0n direction signal polarity -/w -/w

4 1 = clears SD_CH0_STEPCOUNT, user needs to set it back to 0 afterwards -/w -/w

5 0/1: 0 = normal step pulses, 1 = toggle mode -/w -/w

6 1 = use SD_CH0_NEXTSR for SD_CH0_STEPRATE on compare event -/w -/w

7 reserved -/w -/w

8 0/1: 0 = enabled, 1 = disabled SD_CH1 -/w -/w

9 0 = generate N pulses based on SD_CH1_STEPTARGET register value

1 = continuous mode

-/w -/w

10 S1 and S1n step pulse signal polarity -/w -/w

11 D1 and D1n direction signal polarity -/w -/w

12 1 = clears SD_CH1_STEPCOUNT, user needs to set it back to 0 afterwards -/w -/w

13 0/1: 0 = normal step pulses, 1 = toggle mode -/w -/w

14 1 = use SD_CH1_NEXTSR for SD_CH1_STEPRATE on compare event -/w -/w

15 reserved -/w -/w

16 0/1: 0 = enabled, 1 = disabled SD_CH2 -/w -/w

17 0 = generate N pulses based on SD_CH2_STEPTARGET register value

1 = continuous mode

-/w -/w

18 S2 and S2n step pulse signal polarity -/w -/w

19 D2 and D2n direction signal polarity -/w -/w

20 1 = clears SD_CH2_STEPCOUNT, user needs to set it back to 0 afterwards -/w -/w

21 0/1: 0 = normal step pulses, 1 = toggle mode -/w -/w

22 1 = use SD_CH2_NEXTSR for SD_CH2_STEPRATE on compare event -/w -/w

23 reserved -/w -/w

Table 160: MFC IO Register 35 – SD_CFG

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