Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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7.3.4.15 Register 32 – SD_CH2_NEXTSR
Bit Description ECAT PDI Range [Unit]
31:0 Next accumulation constant that will be written
to SD_CH2_STEPRATE at compare event.
-/w -/w 0. . . +(2
32
) − 1
Table 157: MFC IO Register 32 – SD_CH2_NEXTSR
7.3.4.16 Register 33 – SD_STEPLENGTH
Bit Description ECAT PDI Range [Unit]
15:0 Configurable step pulse length for SD_CH0 in
terms of 25MHz clock cycles.
-/w -/w 0. . . +(2
16
) − 1
31:16 Configurable step pulse length for SD_CH1 in
terms of 25MHz clock cycles.
-/w -/w 0. . . +(2
16
) − 1
47:32 Configurable step pulse length for SD_CH2 in
terms of 25MHz clock cycles.
-/w -/w 0. . . +(2
16
) − 1
Table 158: MFC IO Register 33 – SD_STEPLENGTH
Note
Maximum step length: The individual step pulse length t
ST EP _P ULSE
[s] must be
lower than the time t
ST EP
[s] between step pulses to actually see step pulses. The
condition t
ST EP _P ULSE
< t
ST EP
must be ensured by the application.
Also refer to Section 7.14 for more details and formulas for calculation.
7.3.4.17 Register 34 – SD_DELAY
Bit Description ECAT PDI Range [Unit]
15:0 Configurable step-to-direction delay for
SD_CH0 in terms of 25MHz clock cycles.
-/w -/w 0. . . +(2
16
) − 1
31:16 Configurable step-to-direction delay for
SD_CH1 in terms of 25MHz clock cycles.
-/w -/w 0. . . +(2
16
) − 1
47:32 Configurable step-to-direction delay for
SD_CH2 in terms of 25MHz clock cycles.
-/w -/w 0. . . +(2
16
) − 1
Table 159: MFC IO Register 34 – SD_DELAY
Note
Step-to-direction delay is the delay between the first step pulse after a change of
the direction.
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