Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21

118 / 204

7.3.2 SPI Master Interface

7.3.2.1 Register 6 – SPI_RX_DATA

Bit Description ECAT PDI Range [Unit]

63:0 Received data from last SPI transfer

For SPI transfers with less than 64 bit, the upper

bits of this register are unused

r/- r/-

Table 131: MFC IO Register 6 – SPI_RX_DATA

7.3.2.2 Register 7 – SPI_TX_DATA

Bit Description ECAT PDI Range [Unit]

63:0 Data to transmit on next SPI transfer

For SPI transfers with less than 64 bit, the upper

bits of this register are unused

-/w -/w

Table 132: MFC IO Register 7 – SPI_TX_DATA

Note

Unless conﬁgured otherwise in the SPI_CONF register (bits 10:8), writing data

into this register automatically starts transmission as soon as the highest byte

(according to SPI_LENGTH conﬁguration) has been written.

All bytes to be transmitted must be written to the register within a single access

(via MFC IO Control SPI or from the DPRAM) to ensure data consistency.

7.3.2.3 Register 8 – SPI_CONF

Bit Description ECAT PDI Range [Unit]

1:0 Selection of SPI slave r/w r/w

2 reserved r/w r/w

Keep CS low after transfer for transfers greater

than 64bit

r/w r/w

4 transmit LSB ﬁrst r/w r/w

5 SPI clock phase r/w r/w

6 SPI clock polarity r/w r/w

7 reserved r/w r/w

Terms of delivery and rights to technical change reserved.

Download newest version at www.trinamic.com