Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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7.3.1.2 Register 1 – ENC_STATUS
Bit Description ECAT PDI Range [Unit]
0 n_event
1: Encoder N event detected. Status bit is
cleared on read: Read (R) + clear (C)
This event can also be ORed into the interrupt
output signal. See Register 51 and 52.
r+c/- r+c/-
7:1 Reserved r/- r/-
Table 126: MFC IO Register 1 – ENC_STATUS
7.3.1.3 Register 2 – X_ENC (write)
Bit Description ECAT PDI Range [Unit]
31:0 Actual encoder position (signed) r/w r/w −2
31
. . . +(2
31
) − 1
Table 127: MFC IO Register 2 – X_ENC (write)
7.3.1.4 Register 3 – X_ENC (read)
Bit Description ECAT PDI Range [Unit]
31:0 Actual encoder position (signed) r/- r/- −2
31
. . . +(2
31
) − 1
Table 128: MFC IO Register 3 – X_ENC (read)
7.3.1.5 Register 4 – ENC_CONST
Bit Description ECAT PDI Range [Unit]
31:0 Accumulation constant (signed) 16 bit integer
part, 16 bit fractional part
X_ENC accumulates
±
ENC_CON ST
(2
16
∗X_EN C)
(binary)
or
±
ENC_CON ST
(10
4
∗X_EN C)
(decimal)
ENC_MODE bit enc_sel_decimal switches be-
tween decimal and binary setting. Use the sign,
to match rotation direction!
r/w r/w binary:
±[µsteps/2
16
]
±(0 . . . 32767.9999847)
decimal:
±(0 . . . 32767.9999)
reset default = 1 . 0(=
65536)
Table 129: MFC IO Register 4 – ENC_CONST
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