Datasheet

TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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7.3 MFC IO Register Set
7.3.1 Incremental Encoder Interface
7.3.1.1 Register 0 – ENC_MODE
Bit Description ECAT PDI Range [Unit]
0 pol_A
Required A polarity for an N channel event (0: neg., 1: pos.)
r/w r/w
1 pol_B
Required B polarity for an N channel event (0: neg., 1: pos.)
r/w r/w
2 pol_N
Defines active polarity of N (0: neg., 1: pos.)
r/w r/w
3 ignore_AB
0: An N event occurs only when polarities given by pol_N,
pol_A and pol_B match.
1: Ignore A and B polarity for N channel event
r/w r/w
4 clr_cont
1: Always latch or latch and clear X_ENC upon an N event
(once per revolution, it is recommended to combine this
setting with edge sensitive N event)
r/w r/w
5 clr_once
1: Latch or latch and clear X_ENC on the next N event fol-
lowing the write access
r/w r/w
7:6 neg_edge bit n & pos_edge bit p
n p: N channel event sensitivity
0 0 : N channel event is active during an active N event level
0 1: N channel is valid upon active going N event
1 0: N channel is valid upon inactive going N event
1 1 : N channel is valid upon active going and inactive going
N event
r/w r/w
8 clr_enc_x
0: On N event, X_ENC becomes latched to ENC_LATCH only
1: Latch & additionally clear X_ENC at N-event
r/w r/w
9 latch_x_act
1: Also latch XACTUAL position together with X_ENC. Allows
latching the ramp generator position upon an N channel
event as selected by pos_edge and neg_edge.
r/w r/w
10 enc_sel_decimal
0: Encoder prescaler divisor binary mode: Counts
ENC_CONST(fractional part) / 65536
1: Encoder prescaler divisor decimal mode: Counts in
ENC_CONST(fractional part) / 10000
r/w r/w
15:11 Reserved -/- -/-
Table 125: MFC IO Register 0 – ENC_MODE
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