Datasheet
TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21
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6.4.19.5 Latch0 Time Positive Edge (0x09B0:0x09B7)
Bit Description ECAT PDI Reset Value
63:0
Register captures System time at the positive
edge of the Latch0 signal.
r(ack)/-
r/
(w
ack)*
0
Table 113: Register 0x09B0:0x09B7 (Latch0 Time Pos Edge)
Note
Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0]
are read, which guarantees reading a consistent value. Reading this register from
ECAT clears Latch0 Status
0x09AE.0
if
0x0980.4
=0. Writing to this register from
ECAT is not possible.
* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if
0x0980.4=1 clears Latch0 Status 0x09AE.0. Writing to this register from PDI is not possible.
PDI register function acknowledge by Write command is enabled: Writing this register from PDI if
0x0980.4
=1 clears Latch0 Status
0x09AE.0
. Writing to this register from PDI is possible; write value is
ignored (write 0).
6.4.19.6 Latch0 Time Negative Edge (0x09B8:0x09BF)
Bit Description ECAT PDI Reset Value
63:0
Register captures System time at the negative
edge of the Latch0 signal.
r(ack)/-
r/
(w
ack)*
0
Table 114: Register 0x09B8:0x09BF (Latch0 Time Neg Edge)
Note
Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0]
are read, which guarantees reading a consistent value. Reading this register from
ECAT clears Latch0 Status
0x09AE.1
if
0x0980.4
=0. Writing to this register from
ECAT is not possible.
* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if
0x0980.4=1 clears Latch0 Status 0x09AE.1. Writing to this register from PDI is not possible.
PDI register function acknowledge by Write command is enabled: Writing this register from PDI if
0x0980.4
=1 clears Latch0 Status
0x09AE.1
. Writing to this register from PDI is possible; write value is
ignored (write 0).
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